公开(公告)号：US11500446B2

公开(公告)日：2022-11-15

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Shankar Natarajan ,  Chang Wan Ha ,  Chee Law ,  Khaled Hasnat ,  Chuan Lin ,  Shafqat Ahmed

IPC: G06F1/32 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G06F1/3234

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

公开(公告)号：US11322546B2

公开(公告)日：2022-05-03

申请号：US16145084

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Shafqat Ahmed ,  Kiran Pangal

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L27/11507 ,  H01L43/12 ,  H01L43/02 ,  G11C13/00 ,  H01L49/02

Abstract: A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.