公开(公告)号：US20190042162A1

公开(公告)日：2019-02-07

申请号：US16104040

申请日：2018-08-16

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Suneeta SAH ,  George VERGIS ,  Dimitrios ZIAKAS ,  Bill NALE ,  Chong J. ZHAO ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.

公开(公告)号：US20190213148A1

公开(公告)日：2019-07-11

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX ,  Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Chong J. ZHAO ,  Suneeta SAH ,  Pete D. VOGT ,  John R. GOLES

IPC: G06F13/16 ,  G06F13/40 ,  G11C14/00 ,  G11C11/4096

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096 ,  G11C14/0009 ,  Y02D10/14 ,  Y02D10/151

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US20160379690A1

公开(公告)日：2016-12-29

申请号：US15225717

申请日：2016-08-01

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Klaus RUFF ,  George VERGIS ,  Suneeta SAH

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.