公开(公告)号：US20190018809A1

公开(公告)日：2019-01-17

申请号：US16046587

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Bill NALE ,  Raj K. RAMANUJAN ,  Muthukumar P. SWAMINATHAN ,  Tessil THOMAS ,  Taarinya POLEPEDDI

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F9/46 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0804 ,  G06F12/0897 ,  G06F12/0802 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

公开(公告)号：US20170249266A1

公开(公告)日：2017-08-31

申请号：US15482542

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Bill NALE ,  Raj K. RAMANUJAN ,  Muthukuman P. SWAMINATHAN ,  Tessil THOMAS ,  Taarinya POLEPEDDI

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol