公开(公告)号：US09871026B2

公开(公告)日：2018-01-16

申请号：US15068262

申请日：2016-03-11

Applicant: Intel Corporation

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L23/02 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

公开(公告)号：US20160197065A1

公开(公告)日：2016-07-07

申请号：US15068262

申请日：2016-03-11

Applicant: Intel Corporation

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

公开(公告)号：US09287248B2

公开(公告)日：2016-03-15

申请号：US14104877

申请日：2013-12-12

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L23/52 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了允许诸如处理器和存储器的设备之间的相对短的连接的集成电路封装组件。 在一个实施例中，封装组件包括嵌入到直接耦合到附接到子封装的另一管芯的子封装中的管芯。 在一些实施例中，子包还可以包含电源管理装置。 在一些实施例中，嵌入在子封装和/或功率管理器件中的管芯可以与耦合到子封装的管芯定义的区域重叠或位于其中，使得它们位于耦合到子封装的管芯和衬底之间 子包。 可以描述和/或要求保护其他实施例。