公开(公告)号：US20180286840A1

公开(公告)日：2018-10-04

申请号：US15765992

申请日：2015-11-04

Applicant: Intel Corporation

Inventor： Vijay K. NAIR ,  Adel A. ELSHERBINI ,  Lakshman KRISHNAMURTHY ,  Johanna M. SWAN ,  Alexander ESSAIAN ,  Torrey W. FRANK

IPC: H01L25/16 ,  H01L23/498 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L21/568 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19105

Abstract: Embodiments are generally directed to three-dimensional small form factor system in package architecture. An embodiment of an apparatus includes a first package having a first side and an opposite second side, the first package including a plurality of embedded electronic components and one or more embedded via bars, each via bar including a plurality of through vias; and a second package having a first side and an opposite second side, the second package including a plurality of embedded electronic components, wherein a first side of the first package and a second side of second package are coupled together by a plurality of connections, including at least a first connection connecting the second package to a first component of the first package and a second connection connecting the second package to a first via bar of the one or more via bars.