公开(公告)号：US20230197722A1

公开(公告)日：2023-06-22

申请号：US17558026

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Mohit K. HARAN ,  Leonard P. GULER ,  Pratik PATEL ,  Tahir GHANI ,  Anand S. MURTHY ,  Makram ABD EL QADER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface co-planar with a top surface of the gate structure.

公开(公告)号：US20210167209A1

公开(公告)日：2021-06-03

申请号：US16700431

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Rahul PANDEY ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Pratik PATEL

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230317786A1

公开(公告)日：2023-10-05

申请号：US17700215

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Varun MISHRA ,  Tahir GHANI ,  Pratik PATEL ,  Wonil CHUNG ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

公开(公告)号：US20230420456A1

公开(公告)日：2023-12-28

申请号：US17850782

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Imola ZIGONEANU ,  Gilbert DEWEY ,  Anant H. JAHAGIRDAR ,  Harold W. KENNEL ,  Pratik PATEL ,  Anand S. MURTHY ,  Chi-Hing CHOI ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/161 ,  H01L29/167

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.

公开(公告)号：US20230197714A1

公开(公告)日：2023-06-22

申请号：US17556614

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Aryan NAVABI-SHIRAZI ,  Andy Chih-Hung WEI ,  Mauro J. KOBRINSKY ,  Shaun MILLS ,  Pratik PATEL

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/40

CPC classification number: H01L27/088 ,  H01L27/1203 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/401

Abstract: Gate-all-around integrated circuit structures having backside contact self-aligned to epitaxial source or drain region are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. A conductive structure is vertically beneath and in contact with one of the first epitaxial source or drain structures.

公开(公告)号：US20230420512A1

公开(公告)日：2023-12-28

申请号：US17850778

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Xinning WANG ,  Nischal ARKALI RADHAKRISHNA ,  Leonard P. GULER ,  Mauro J. KOBRINSKY ,  June CHOI ,  Pratik PATEL ,  Tahir GHANI

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/481 ,  H01L29/42392

Abstract: Integrated circuit structures having backside power staple are described. In an example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts is extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A front-side metal routing layer is extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts. A backside metal routing layer is extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer. A conductive feedthrough structure couples the backside metal routing layer to the front-side metal routing layer.

公开(公告)号：US20230420360A1

公开(公告)日：2023-12-28

申请号：US17850779

申请日：2022-06-27

Applicant: INTEL CORPORATION

Inventor： Mohit HARAN ,  Sukru YEMENICIOGLU ,  Pratik PATEL ,  Charles H. WALLACE ,  Leonard P. GULER ,  Conor P. PULS ,  Makram ABD EL QADER ,  Tahir GHANI

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC classification number: H01L23/5226 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L27/11807 ,  H01L23/5283

Abstract: Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

公开(公告)号：US20230131126A1

公开(公告)日：2023-04-27

申请号：US18088469

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Rahul PANDEY ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Pratik PATEL

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20210408275A1

公开(公告)日：2021-12-30

申请号：US16913307

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Suresh VISHWANATH ,  Pratik PATEL ,  Szuya S. LIAO ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49

Abstract: Integrated circuit structures having high surface germanium concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure has an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure has an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures.

公开(公告)号：US20210407851A1

公开(公告)日：2021-12-30

申请号：US16913320

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Suresh VISHWANATH ,  Yulia TOLSTOVA ,  Pratik PATEL ,  Szuya S. LIAO ,  Anand S. MURTHY

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/08 ,  H01L29/66

Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.