公开(公告)号：US20180032429A1

公开(公告)日：2018-02-01

申请号：US15224134

申请日：2016-07-29

Applicant: Intel Corporation

Inventor： Min LIU ,  Zhenlin LUO ,  George VERGIS ,  Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Ross E. ZWISLER

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0871 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/023 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/202 ,  G06F2212/205 ,  G06F2212/222 ,  G06F2212/225 ,  G06F2212/271 ,  G06F2212/305 ,  G06F2212/604

Abstract: A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.