公开(公告)号：US20180374835A1

公开(公告)日：2018-12-27

申请号：US15777810

申请日：2015-12-25

Applicant: Intel Corporation

Inventor： Zhicheng DING ,  Bin LIU

IPC: H01L25/16 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/66

Abstract: A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

公开(公告)号：US20210057326A1

公开(公告)日：2021-02-25

申请号：US17053144

申请日：2018-12-12

Applicant: INTEL CORPORATION

Inventor： Zhicheng DING ,  Bin LIU ,  Yong SHE ,  Zhijun XU

IPC: H01L23/525 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

公开(公告)号：US20220093568A1

公开(公告)日：2022-03-24

申请号：US17424839

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Jianfeng HU ,  Zhicheng DING ,  Yong SHE ,  Zhijun XU

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a plurality of cavities, and a plurality of adhesives in the cavities of the package substrate. The semiconductor package also includes a plurality of stacked dies over the adhesives and the package substrate, where the stacked dies are coupled to the adhesives with spacers. The spacers may be positioned below outer edges of the stacked dies. The adhesives may include a plurality of films. The semiconductor package may further include a plurality of interconnects coupled to the stacked dies and package substrate, a plurality of electrical components on the package substrate, a mold layer over the stacked dies, interconnects, spacers, adhesives, and electrical components, and a plurality of adhesive layers coupled to the plurality of stacked dies, where one of the adhesive layers couples the stacked dies to the spacers.

公开(公告)号：US20190019777A1

公开(公告)日：2019-01-17

申请号：US15749760

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Yong SHE ,  John G. MEYERS ,  Zhicheng DING ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/49 ,  H01L23/00 ,  H01L23/50 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/488 ,  H01L23/49 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48249 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83007 ,  H01L2224/92174 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.