公开(公告)号：US20200066621A1

公开(公告)日：2020-02-27

申请号：US15752240

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Bin LIU ,  John G. MEYERS ,  Florence R. PON

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00

Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.

公开(公告)号：US20160324487A1

公开(公告)日：2016-11-10

申请号：US14779513

申请日：2014-11-27

Applicant: INTEL CORPORATION

Inventor： Mao GUO ,  Junfeng ZHAO ,  Michael P. SKINNER ,  Ke XIAO ,  Jiamiao TANG ,  Bin LIU ,  Li DENG

IPC: A61B5/00 ,  G08B5/22 ,  A61B7/00 ,  A61B5/107 ,  A61B5/11 ,  H04Q9/00 ,  A61B5/08

CPC classification number: A61B5/746 ,  A61B5/0022 ,  A61B5/0816 ,  A61B5/1072 ,  A61B5/1118 ,  A61B5/4815 ,  A61B5/486 ,  A61B5/6804 ,  A61B5/6823 ,  A61B5/6831 ,  A61B5/7405 ,  A61B5/7455 ,  A61B7/00 ,  A61B2562/0219 ,  A61B2562/0247 ,  A61B2562/04 ,  A61B2562/063 ,  A61B2562/166 ,  G08B3/10 ,  G08B5/224 ,  G08B6/00 ,  G08B21/0269 ,  G08B21/0277 ,  G08B21/0283 ,  H04Q9/00 ,  H04Q2209/43

Abstract: Embodiments described herein may fully integrate personal computing and health care into a wearable waistband having a length sensor, a pressure sensor, and a motion sensor; or into a wearable “mesh” having an array of sound sensors, which will create convenient and seamless access to a personal computer and biofeedback of the wearer. Such biofeedback from the waistband may include determining respiration rate, waist length, food quantity of a meal, sitting or sleep time, and frequency of visits to the bathroom. Such biofeedback from the mesh or array may include determining whether there is or has been damage or other issues of the heart, lungs, bones, joints, jaw, throat, arteries, digestive tract, and the like. Such biofeedback may also detect whether whether a person has an allergic reaction at a location, is drinking (and what volume of fluid), is walking, is jogging or is running.

Abstract translation: 本文描述的实施例可以将个人计算和健康护理完全集成到具有长度传感器，压力传感器和运动传感器的可穿戴腰带中; 或具有声音传感器阵列的可穿戴的“网状”，其将创建便利且无缝地访问个人计算机和穿戴者的生物反馈。 来自腰带的这种生物反馈可以包括确定呼吸速率，腰围长度，膳食的食物数量，坐着或睡眠时间以及访问浴室的频率。 来自网状物或阵列的这种生物反馈可以包括确定是否存在心脏，肺，骨骼，关节，下颌，咽喉，动脉，消化道等的损伤或其它问题。 这种生物反馈还可以检测一个人是否在某个地点发生过敏反应，正在饮酒（以及什么体积的流体）正在步行，正在慢跑或跑步。

公开(公告)号：US20220122907A1

公开(公告)日：2022-04-21

申请号：US17425227

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Xiaoying TANG ,  200241 DING ,  Bin LIU ,  Yong SHE ,  Zhijun XU

IPC: H01L23/498 ,  H01L23/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

公开(公告)号：US20180331004A1

公开(公告)日：2018-11-15

申请号：US15772483

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Mao GUO ,  John G. MEYERS ,  Yong SHE ,  Bin LIU ,  Lingyan L. TAN

IPC: H01L23/28 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/28 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).

公开(公告)号：US20180374835A1

公开(公告)日：2018-12-27

申请号：US15777810

申请日：2015-12-25

Applicant: Intel Corporation

Inventor： Zhicheng DING ,  Bin LIU

IPC: H01L25/16 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/66

Abstract: A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.

公开(公告)号：US20230163045A1

公开(公告)日：2023-05-25

申请号：US17919730

申请日：2020-05-19

Applicant: INTEL CORPORATION

Inventor： Bin LIU ,  Fen YI

IPC: H01L23/373 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/3737 ,  H01L24/32 ,  H01L24/33 ,  H01L25/0657 ,  H01L25/0655 ,  H01L21/481 ,  H01L2224/32225 ,  H01L24/48 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L24/73 ,  H01L2224/73265 ,  H01L2224/33181 ,  H01L2224/32145 ,  H01L2224/73215 ,  H01L2225/06562 ,  H01L23/49827

Abstract: Embodiments of the present disclosure are directed to organic spacers for integrated circuits. Among other things, the organic spacers of the embodiments of the present disclosure help provide a cost-efficient and effective solution to address issues such as coefficient of thermal expansion (CTE) mismatches, dynamic warpage, and solder joint reliability (SJR). Other embodiments may be described and claimed.

公开(公告)号：US20210057326A1

公开(公告)日：2021-02-25

申请号：US17053144

申请日：2018-12-12

Applicant: INTEL CORPORATION

Inventor： Zhicheng DING ,  Bin LIU ,  Yong SHE ,  Zhijun XU

IPC: H01L23/525 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.