公开(公告)号：US20200014397A1

公开(公告)日：2020-01-09

申请号：US16474582

申请日：2017-03-31

Applicant: Intel IP Corporation

Inventor： Antonio Passamani

IPC: H03M1/66 ,  H04B1/04 ,  H04B1/00

Abstract: A mapping circuit (300) for selecting cells of a multi core hybrid I/Q digital to analog converter includes a first sub-mapping circuit (310a) configured to define a first group of cores for each data symbol to be transmitted and to select cells of the first group of cores for an I-code of the data symbol to be transmitted. The mapping circuit (310b) further includes a second sub-mapping circuit configured to define a second group of cores for each data symbol and to select cells of the second group of cores for a Q-code of the data symbol.

公开(公告)号：US10797719B2

公开(公告)日：2020-10-06

申请号：US16474582

申请日：2017-03-31

Applicant: Intel IP Corporation

Inventor： Antonio Passamani

IPC: H03M1/66 ,  H04B1/02 ,  H04B1/00 ,  H04B1/04

Abstract: A mapping circuit (300) for selecting cells of a multi core hybrid I/Q digital to analog converter includes a first sub-mapping circuit (310a) configured to define a first group of cores for each data symbol to be transmitted and to select cells of the first group of cores for an I-code of the data symbol to be transmitted. The mapping circuit (310b) further includes a second sub-mapping circuit configured to define a second group of cores for each data symbol and to select cells of the second group of cores for a Q-code of the data symbol.

公开(公告)号：US09819356B2

公开(公告)日：2017-11-14

申请号：US14570299

申请日：2014-12-15

Applicant: Intel IP Corporation

Inventor： Davide Ponton ,  Antonio Passamani ,  Andrea Bevilacqua

IPC: H03M1/66 ,  H04L27/233 ,  H03C3/00 ,  H03M1/82 ,  H03K3/03 ,  G04F10/00 ,  H03L7/099 ,  H03K5/131

CPC classification number: H03M1/662 ,  G04F10/005 ,  H03C3/00 ,  H03K3/0315 ,  H03K5/131 ,  H03L7/0998 ,  H03M1/82 ,  H04L27/2331

Abstract: Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

公开(公告)号：US09647678B2

公开(公告)日：2017-05-09

申请号：US15240462

申请日：2016-08-18

Applicant: Intel IP Corporation

Inventor： Antonio Passamani ,  Franz Kuttner ,  Michael Fulde

IPC: H03M1/66 ,  H04L27/00 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03M1/74 ,  H04L27/00 ,  H04L27/0002

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

公开(公告)号：US20170093422A1

公开(公告)日：2017-03-30

申请号：US15240462

申请日：2016-08-18

Applicant: Intel IP Corporation

Inventor： Antonio Passamani ,  Franz Kuttner ,  Michael FULDE

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/74 ,  H04L27/00 ,  H04L27/0002

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

公开(公告)号：US09571120B2

公开(公告)日：2017-02-14

申请号：US14835031

申请日：2015-08-25

Applicant: Intel IP Corporation

Inventor： Franz Kuttner ,  Antonio Passamani ,  Davide Ponton

IPC: H03M1/66 ,  H03M1/74 ,  H03M1/00 ,  H03M1/12 ,  H03M3/00

CPC classification number: H03M1/662 ,  H03M1/00 ,  H03M1/12 ,  H03M1/74 ,  H03M1/747 ,  H03M3/30

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract translation: 数模转换器电路包括多个数模转换器单元。 数模转换器电路还包括控制电路，其被配置为基于数字信号的第一相位分量来控制多个数模转换器单元中的数模转换器单元的操作，该数字信号包括将在第一 时间间隔，并且基于数字信号的第二相位分量，包括将在第二时间间隔期间发送的信息。

公开(公告)号：US20160094235A1

公开(公告)日：2016-03-31

申请号：US14835031

申请日：2015-08-25

Applicant: Intel IP Corporation

Inventor： Franz Kuttner ,  Antonio Passamani ,  Davide Ponton

IPC: H03M1/00 ,  H03M1/74

CPC classification number: H03M1/662 ,  H03M1/00 ,  H03M1/12 ,  H03M1/74 ,  H03M1/747 ,  H03M3/30

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract translation: 数模转换器电路包括多个数模转换器单元。 数模转换器电路还包括控制电路，其被配置为基于数字信号的第一相位分量来控制多个数模转换器单元中的数模转换器单元的操作，该数字信号包括将在第一 时间间隔，并且基于数字信号的第二相位分量，包括将在第二时间间隔期间发送的信息。