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    QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING
    2.
    发明公开
    QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING 审中-公开

    公开(公告)号：US20240097872A1

    公开(公告)日：2024-03-21

    申请号：US17933557

    申请日：2022-09-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Michael Sperling ,  Daniel Mark Dreps ,  Erik English ,  Jieming Qi

    IPC分类号： H04L7/00 ,  H04L25/24

    CPC分类号： H04L7/0012 ,  H04L25/247

    摘要： An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

    Calibrating a quadrature receive serial interface
    4.
    发明授权
    Calibrating a quadrature receive serial interface 有权

    公开(公告)号：US11973630B1

    公开(公告)日：2024-04-30

    申请号：US18059264

    申请日：2022-11-28

    申请人： International Business Machines Corporation

    发明人： Michael B. Spear ,  Daniel Mark Dreps ,  Erik English ,  Jieming Qi ,  Michael Sperling

    IPC分类号： H04L27/00 ,  H04L27/36

    CPC分类号： H04L27/364 ,  H04L27/0014 ,  H04L2027/0018

    摘要： An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.

    Communication systems for power supply noise reduction
    7.
    发明授权
    Communication systems for power supply noise reduction 有权

    公开(公告)号：US12095891B2

    公开(公告)日：2024-09-17

    申请号：US17938850

    申请日：2022-10-07

    申请人： International Business Machines Corporation

    发明人： David J. Krolak ,  Daniel Mark Dreps ,  Erik English ,  Jieming Qi ,  Michael Sperling

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0012

    摘要： Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

    Quadrature circuit interconnect architecture with clock forwarding
    8.
    发明授权
    Quadrature circuit interconnect architecture with clock forwarding 有权

    公开(公告)号：US11979480B2

    公开(公告)日：2024-05-07

    申请号：US17933557

    申请日：2022-09-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Michael Sperling ,  Daniel Mark Dreps ,  Erik English ,  Jieming Qi

    IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/24 ,  H04L25/40

    CPC分类号： H04L7/0012 ,  H04L25/247

    摘要： An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.