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公开(公告)号：US20240008186A1
公开(公告)日：2024-01-04
申请号：US17854766
申请日：2022-06-30
发明人： Yanyan Zhang , Mahesh Bohra , Wiren Dale Becker , Nam Huu Pham , Pavel Roy Paladhi , Daniel Mark Dreps , Lloyd Andre Walls
CPC分类号： H05K3/0047 , H05K3/429 , H05K1/115
摘要： A gang drilling machine for drilling a circuit card includes a pair of n and p master drills that are configured to be aligned in registry with respective n and p test vias of the card; pluralities of n and p minion drills that are configured to be aligned in registry with pluralities of n and p live vias of the card; and a controller that is electrically connected to control the n and p master drills and minion drills, and to send and receive electrical signals to and from the card. The controller is configured to: send a query signal to the card; monitor a response signal from the card; determine drilling depth of at least one of the master drills, in response to comparing the response signal to the query signal; and adjust operation of the machine, in response to the determined drilling depth.
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2.发明授权System interconnect dynamic scaling by lane width and operating frequency balancing 有权通过车道宽度和工作频率平衡进行系统互连动态缩放公开(公告)号：US09529406B2
公开(公告)日：2016-12-27
申请号：US14302628
申请日：2014-06-12
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency.
摘要翻译： 接口管理技术在具有多个互连处理单元的计算机系统中提供降低的功率消耗以及减少热和EMI产生。 互连处理单元的外部接口的物理链路层具有由可调节宽度和可调工作频率提供的动态可调节带宽。 可以通过预测接口带宽要求来动态调整带宽。 从所需带宽，确定和设置物理链路层的有效宽度和工作频率。 接口根据确定的宽度和工作频率进行操作。
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公开(公告)号：US09459982B2
公开(公告)日：2016-10-04
申请号：US14299319
申请日：2014-06-09
CPC分类号： G06F11/3041 , G06F11/2002 , G06F11/2007 , G06F11/2033 , G06F11/2038 , G06F11/221 , G06F11/24 , G06F11/3027 , G06F11/34 , G06F11/3409 , G06F11/3466 , G06F11/3485 , G06F11/349
摘要： A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.
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公开(公告)号：US09324031B2
公开(公告)日：2016-04-26
申请号：US14299415
申请日：2014-06-09
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman , David John Krolak
CPC分类号： G06N7/005 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F9/45558 , G06F2009/45579 , G06F2009/45591 , Y02D10/157
摘要： Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface control method detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The method predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.
摘要翻译： 接口管理技术在具有多个互连处理单元的计算机系统中提供降低的功率消耗以及减少热和EMI产生。 通过预测接口带宽需求动态调整互连具有动态可调节带宽和带宽的处理单元的外部接口的物理链路层。 接口控制方法检测在作为连接到处理单元的外部接口之一上的潜在未来事务的指示符的处理单元中发生的I / O请求之外的事件。 该方法从检测到的事件中预测未来的事务可能在接口上发生，并且作为响应，控制接口的物理链路层的动态可调节带宽以适应未来的事务。
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公开(公告)号：US11973630B1
公开(公告)日：2024-04-30
申请号：US18059264
申请日：2022-11-28
CPC分类号： H04L27/364 , H04L27/0014 , H04L2027/0018
摘要： An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.
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公开(公告)号：US09324030B2
公开(公告)日：2016-04-26
申请号：US14147746
申请日：2014-01-06
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman , David John Krolak
CPC分类号： G06N7/005 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F9/45558 , G06F2009/45579 , G06F2009/45591 , Y02D10/157
摘要： Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface controller detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The interface controller predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.
摘要翻译： 接口管理技术在具有多个互连处理单元的计算机系统中提供降低的功率消耗以及减少热和EMI产生。 通过预测接口带宽需求动态调整互连具有动态可调节带宽和带宽的处理单元的外部接口的物理链路层。 接口控制器检测在处理单元中发生的I / O请求之外的事件，这些事件是连接到处理单元的外部接口之一上的潜在未来事务的指示符。 接口控制器从检测到的事件中预测将来的事务可能在接口上发生，并且作为响应，控制接口的物理链路层的动态可调节带宽以适应未来的事务。
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7.发明授权Bus interface optimization by selecting bit-lanes having best performance margins 有权通过选择具有最佳性能余量的位线，实现总线接口优化公开(公告)号：US09244799B2
公开(公告)日：2016-01-26
申请号：US14147732
申请日：2014-01-06
CPC分类号： G06F11/3041 , G06F11/2002 , G06F11/2007 , G06F11/2033 , G06F11/2038 , G06F11/221 , G06F11/24 , G06F11/3027 , G06F11/34 , G06F11/3409 , G06F11/3466 , G06F11/3485 , G06F11/349
摘要： A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.
摘要翻译： 总线接口通过在总线接口的初始化或校准期间测试各个位通道的性能余量，选择位线作为备件进行分配。 评估各个位通道的性能余量，因为接口的工作频率增加，直到满足指定性能余量的剩余位数等于接口所需的宽度为止。 不满足所需性能余量的位线被分配为备件，并且接口可以以最高的评估工作频率运行。 当操作位通道发生故障时，其中一个备用位通道被分配为替换位通道，并且接口工作频率降低到新的一组操作位通道满足性能裕度的频率。 界面的工作频率可以在运行期间动态增加和减少，并且评估性能余量以优化性能。
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公开(公告)号：US20150193690A1
公开(公告)日：2015-07-09
申请号：US14147746
申请日：2014-01-06
发明人： Daniel Mark Dreps , Frank D. Ferraiolo , Anand Haridass , Prasanna Jayaraman , David John Krolak
CPC分类号： G06N7/005 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F9/45558 , G06F2009/45579 , G06F2009/45591 , Y02D10/157
摘要： Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface controller detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The interface controller predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.
摘要翻译： 接口管理技术在具有多个互连处理单元的计算机系统中提供降低的功率消耗以及减少热和EMI产生。 通过预测接口带宽需求动态调整互连具有动态可调节带宽和带宽的处理单元的外部接口的物理链路层。 接口控制器检测在处理单元中发生的I / O请求之外的事件，这些事件是连接到处理单元的外部接口之一上的潜在未来事务的指示符。 接口控制器从检测到的事件中预测将来的事务可能在接口上发生，并且作为响应，控制接口的物理链路层的动态可调节带宽以适应未来的事务。
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9.发明申请BUS INTERFACE OPTIMIZATION BY SELECTING BIT-LANES HAVING BEST PERFORMANCE MARGINS 有权通过选择具有最佳性能标记的位置的总线接口优化公开(公告)号：US20150193287A1
公开(公告)日：2015-07-09
申请号：US14147732
申请日：2014-01-06
CPC分类号： G06F11/3041 , G06F11/2002 , G06F11/2007 , G06F11/2033 , G06F11/2038 , G06F11/221 , G06F11/24 , G06F11/3027 , G06F11/34 , G06F11/3409 , G06F11/3466 , G06F11/3485 , G06F11/349
摘要： A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.
摘要翻译： 总线接口通过在总线接口的初始化或校准期间测试各个位通道的性能余量，选择位线作为备件进行分配。 评估各个位通道的性能余量，因为接口的工作频率增加，直到满足指定性能余量的剩余位数等于接口所需的宽度为止。 不满足所需性能余量的位线被分配为备件，并且接口可以以最高的评估工作频率运行。 当操作位通道发生故障时，其中一个备用位通道被分配为替换位通道，并且接口工作频率降低到新的一组操作位通道满足性能裕度的频率。 界面的工作频率可以在运行期间动态增加和减少，并且评估性能余量以优化性能。
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公开(公告)号：US12095891B2
公开(公告)日：2024-09-17
申请号：US17938850
申请日：2022-10-07
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.
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