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    BITLINE DELETION
    1.
    发明申请
    BITLINE DELETION 有权

    公开(公告)号：US20130339809A1

    公开(公告)日：2013-12-19

    申请号：US13788744

    申请日：2013-03-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

    IPC: G06F11/08

    CPC classification number: G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

    Abstract: Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses.

    Abstract translation: 实施例涉及用于位线删除的计算机系统，该系统包括高速缓存控制器和高速缓存。 该系统被配置为执行一种方法，包括当读取第一高速缓存线时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误，记录第二错误的第二地址，比较 第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三高速缓存线时检测第三错误，记录第三位线地址 将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和匹配的第三和第二位线地址来删除与第三高速缓存线对应的位置。

    MEMORY ARRAY ELEMENT SPARING
    2.
    发明申请
    MEMORY ARRAY ELEMENT SPARING 审中-公开

    公开(公告)号：US20200264803A1

    公开(公告)日：2020-08-20

    申请号：US16280577

    申请日：2019-02-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Tim Bronson ,  Hieu T. Huynh ,  Kenneth Klapproth

    IPC: G06F3/06 ,  G06F12/0895

    Abstract: Methods, systems and computer program products for providing access to a spare memory array element (“MAE”) are provided. Aspects include storing a row number a column number associated with a defective MAE of a plurality of MAEs. The plurality of MAEs are logically arranged in a plurality of rows and a plurality of columns. Aspects also include receiving a command to access a cache line. The cache line corresponds to a selected row of MAEs of the plurality of MAEs. Responsive to determining that the selected row matches the row number that is associated with the defective MAE, aspects include activating one or more column shifters to prevent access to the defective MAE and provide access to a spare MAE when accessing the cache line. The activation of the one of more column shifters is based on the column number that is associated with the defective MAE.

    EDRAM MACRO DISABLEMENT IN CACHE MEMORY
    4.
    发明申请
    EDRAM MACRO DISABLEMENT IN CACHE MEMORY 失效
    EDRAM在缓存中的宏指令

    公开(公告)号：US20130042144A1

    公开(公告)日：2013-02-14

    申请号：US13655088

    申请日：2012-10-18

    Applicant: International Business Machines Corporation

    Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Hieu T. Huynh ,  Pak-kin Mak

    IPC: G06F11/26 ,  G06F11/27

    CPC classification number: G11C29/08 ,  G06F11/1666 ,  G06F11/20 ,  G11C11/401 ,  G11C29/883 ,  G11C2029/0401

    Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.

    Abstract translation: 嵌入式动态随机存取存储器（EDRAM）宏禁用的计算机实现方法。 该方法包括隔离高速缓存存储体的EDRAM宏，该高速缓存存储体被划分成多个EDRAM宏的至少三行，该EDRAM宏与至少三行之一相关联。 EDRAM宏的每一行被迭代测试，测试包括尝试在EDRAM宏的每一行进行至少一次写入操作。 确定在测试期间发生错误。 基于确定，禁用与EDRAM宏相关联的整行EDRAM宏的写入。

    Bitline deletion
    6.
    发明授权
    Bitline deletion 有权
    位线删除

    公开(公告)号：US09086990B2

    公开(公告)日：2015-07-21

    申请号：US13788744

    申请日：2013-03-07

    Applicant: International Business Machines Corporation

    Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

    IPC: G06F11/00 ,  G11C29/00 ,  G06F11/10 ,  G06F11/08 ,  G06F11/07 ,  G11C29/12

    CPC classification number: G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

    Abstract: Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses.

    Abstract translation: 实施例涉及用于位线删除的计算机系统，该系统包括高速缓存控制器和高速缓存。 该系统被配置为执行一种方法，包括当读取第一高速缓存线时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误，记录第二错误的第二地址，比较 第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三高速缓存线时检测第三错误，记录第三位线地址 将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和匹配的第三和第二位线地址来删除与第三高速缓存线对应的位置。

    STORING DATA IN A SYSTEM MEMORY FOR A SUBSEQUENT CACHE FLUSH
    7.
    发明申请
    STORING DATA IN A SYSTEM MEMORY FOR A SUBSEQUENT CACHE FLUSH 有权
    存储用于后续缓存的系统存储器中的数据

    公开(公告)号：US20140082289A1

    公开(公告)日：2014-03-20

    申请号：US14086308

    申请日：2013-11-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Hieu T. Huynh ,  Kenneth D. Klapproth ,  Pak-Kin Mak ,  Vesselina K. Papazova

    IPC: G06F12/08

    CPC classification number: G06F12/0895 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0891 ,  G06F12/128

    Abstract: Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.

    Abstract translation: 实施例涉及将数据存储到系统存储器。 一个方面包括通过步进引擎访问具有多个目录条目的高速缓存目录的连续条目，其中对高速缓存目录的访问被给予比其他高速缓存操作更低的优先级。 确定高速缓存目录中的特定目录条目具有指示其被修改的改变行状态。 执行存储操作以将特定对应的高速缓存条目的副本作为高速缓存管理功能的一部分发送到系统存储器。 特定目录条目被更新以指示改变线状态是未修改的。

    Memory array element sparing
    8.
    发明授权
    Memory array element sparing 有权

    公开(公告)号：US11221794B2

    公开(公告)日：2022-01-11

    申请号：US16280577

    申请日：2019-02-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Tim Bronson ,  Hieu T. Huynh ,  Kenneth Klapproth

    IPC: G06F3/06 ,  G06F12/0895

    Abstract: Methods, systems and computer program products for providing access to a spare memory array element (“MAE”) are provided. Aspects include storing a row number a column number associated with a defective MAE of a plurality of MAEs. The plurality of MAEs are logically arranged in a plurality of rows and a plurality of columns. Aspects also include receiving a command to access a cache line. The cache line corresponds to a selected row of MAEs of the plurality of MAEs. Responsive to determining that the selected row matches the row number that is associated with the defective MAE, aspects include activating one or more column shifters to prevent access to the defective MAE and provide access to a spare MAE when accessing the cache line. The activation of the one of more column shifters is based on the column number that is associated with the defective MAE.

    EVACUATION OF MEMORY FROM A DRAWER IN A LIVE MULTI-NODE SYSTEM
    9.
    发明申请
    EVACUATION OF MEMORY FROM A DRAWER IN A LIVE MULTI-NODE SYSTEM 审中-公开

    公开(公告)号：US20200264797A1

    公开(公告)日：2020-08-20

    申请号：US16280641

    申请日：2019-02-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jason D. Kohl ,  Tim Bronson ,  Hieu T. Huynh ,  Michael Andrew Blake

    IPC: G06F3/06

    Abstract: Methods, systems and computer program products for evacuating memory from a drawer in a live multi-node system are provided. Aspects include placing a first drawer into an evacuation mode. The evacuation mode includes a cessation of non-evacuation operations and provides for a transfer of data stored by memory of the first drawer to a destination drawer using dynamic memory reallocation (DMR). Aspects also include transmitting a store request by the first drawer to the destination drawer. The store request represents a request to transfer the data stored by the memory of the first drawer to the destination drawer for storage by the destination drawer. Aspects also include transmitting the data stored by the memory of the first drawer to the destination drawer. The data is transmitted by the first drawer using a local pool of fetch/store controllers.

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