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公开(公告)号：US09876075B2
公开(公告)日：2018-01-23
申请号：US14885771
申请日：2015-10-16
IPC分类号： H01L21/31 , H01L29/06 , H01L21/768 , H01L21/265 , H01L21/02 , H01L21/3213 , H01L21/324 , H01L21/311 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/764
CPC分类号： H01L29/0649 , H01L21/02164 , H01L21/265 , H01L21/31 , H01L21/31144 , H01L21/3213 , H01L21/324 , H01L21/764 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76877 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L23/5329 , H01L23/53295
摘要： Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.
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公开(公告)号：US20170110361A1
公开(公告)日：2017-04-20
申请号：US14885771
申请日：2015-10-16
IPC分类号： H01L21/768 , H01L21/265 , H01L21/02 , H01L21/3213 , H01L29/06 , H01L21/311 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/764 , H01L21/31 , H01L21/324
CPC分类号： H01L29/0649 , H01L21/02164 , H01L21/265 , H01L21/31 , H01L21/31144 , H01L21/3213 , H01L21/324 , H01L21/764 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76877 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L23/5329 , H01L23/53295
摘要： Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.
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公开(公告)号：US20210118722A1
公开(公告)日：2021-04-22
申请号：US17133975
申请日：2020-12-24
发明人： Kenneth Chun Kuen Cheng , Koichi Motoyama , Oscar Van der Straten , Joseph F. Maniscalco , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , H01L29/06 , H01L23/498 , H01L21/764
摘要： A semiconductor structure includes a substrate. A first metallization layer is disposed on the substrate. A second metallization layer is disposed on the first metallization layer and having one or more openings, wherein at least one of the one or more openings is configured to expose a top surface of the first metallization layer. A polymer-adhering liner layer is disposed on sidewalls of the at least one of the one more openings in the second metallization layer. A dielectric polymer is disposed in the at least one of the one or more openings in the second metallization layer and on the polymer-adhering liner layer. The dielectric polymer is configured to seal an air gap in the dielectric polymer.
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公开(公告)号：US20210104406A1
公开(公告)日：2021-04-08
申请号：US16593392
申请日：2019-10-04
IPC分类号： H01L21/24 , H01L21/324 , H01L21/768 , H01L21/304 , H01L21/04
摘要： An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.
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公开(公告)号：US10008563B2
公开(公告)日：2018-06-26
申请号：US15402929
申请日：2017-01-10
IPC分类号： H01L29/06 , H01L21/768 , H01L21/31 , H01L21/265 , H01L21/02 , H01L21/3213 , H01L21/324 , H01L21/311 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/764
CPC分类号： H01L29/0649 , H01L21/02164 , H01L21/265 , H01L21/31 , H01L21/31144 , H01L21/3213 , H01L21/324 , H01L21/764 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76877 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L23/5329 , H01L23/53295
摘要： Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.
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公开(公告)号：US20170117357A1
公开(公告)日：2017-04-27
申请号：US15402929
申请日：2017-01-10
IPC分类号： H01L29/06 , H01L21/768 , H01L23/528
CPC分类号： H01L29/0649 , H01L21/02164 , H01L21/265 , H01L21/31 , H01L21/31144 , H01L21/3213 , H01L21/324 , H01L21/764 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76877 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L23/5329 , H01L23/53295
摘要： Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.
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