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    Stacked FET SRAM
    1.
    发明授权
    Stacked FET SRAM 有权

    公开(公告)号：US11895818B2

    公开(公告)日：2024-02-06

    申请号：US17660640

    申请日：2022-04-26

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Ruilong Xie ,  Carl Radens ,  Junli Wang ,  Ravikumar Ramachandran ,  Julien Frougier ,  Dechao Guo

    IPC分类号： H10B10/00 ,  G11C11/412

    CPC分类号： H10B10/12 ,  G11C11/412

    摘要： Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

    Preserving channel strain in fin cuts
    3.
    发明授权
    Preserving channel strain in fin cuts 有权

    公开(公告)号：US10128239B2

    公开(公告)日：2018-11-13

    申请号：US15294906

    申请日：2016-10-17

    申请人： International Business Machines Corporation

    发明人： Andrew M. Greene ,  Dechao Guo ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

    IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/306

    摘要： A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.

    Contact first replacement metal gate
    7.
    发明授权
    Contact first replacement metal gate 有权
    联系首选替换金属门

    公开(公告)号：US09496362B1

    公开(公告)日：2016-11-15

    申请号：US14987075

    申请日：2016-01-04

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai

    IPC分类号： H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L21/768 ,  H01L21/283

    CPC分类号： H01L29/495 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/76897 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628 ,  H01L29/78

    摘要： A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on source-drain areas between the sacrificial gates. A contact liner and contact material are deposited. The liner and the contact material are removed from above the sacrificial gates. Contact areas are blocked with one or more masking materials and etched. The masking material is removed. The contact material is partially recessed and a nitride liner deposited. An oxide layer is deposited and the sacrificial gate is removed. A metal gate is formed on the channel region and recessed. Insulator material and metal gate material are recessed and a cap is formed over the gate.

    摘要翻译： 技术涉及形成半导体器件。 牺牲栅极形成在衬底的沟道区上。 在牺牲栅极之间的源极 - 漏极区域上生长外延层。 存放接触衬垫和接触材料。 衬垫和接触材料从牺牲栅极上方移除。 接触区域被一种或多种掩模材料堵塞并蚀刻。 去除掩蔽材料。 接触材料部分凹陷并沉积氮化物衬垫。 沉积氧化物层并除去牺牲栅极。 金属栅极形成在沟道区域上并凹陷。 绝缘体材料和金属栅极材料是凹陷的并且在栅极上形成盖。

    PARTIAL SPACER FOR INCREASING SELF ALIGNED CONTACT PROCESS MARGINS
    9.
    发明申请
    PARTIAL SPACER FOR INCREASING SELF ALIGNED CONTACT PROCESS MARGINS 有权
    用于增加自对准接触过程的部分间距

    公开(公告)号：US20160181392A1

    公开(公告)日：2016-06-23

    申请号：US14576436

    申请日：2014-12-19

    申请人： International Business Machines Corporation

    发明人： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

    IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L29/417

    CPC分类号： H01L21/76897 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/3212 ,  H01L21/76829 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

    摘要： A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

    摘要翻译： 提供半导体结构。 半导体在基板上包括栅极堆叠。 半导体包括在栅极叠层的相对侧壁上的第一组侧壁间隔物。 所述半导体包括在所述衬底上的可流动电介质层，其覆盖所述第一组侧壁间隔物的至少一部分。 半导体包括邻近第一组侧壁间隔件的第二组侧壁间隔件，其覆盖其上部，第二组侧壁间隔件直接位于可流动介电层的顶部上。 半导体包括邻近第二组侧壁间隔物中的至少一个的接触。

    MULTIPLE THICKNESS GATE DIELECTRICS FOR REPLACEMENT GATE FIELD EFFECT TRANSISTORS
    10.
    发明申请
    MULTIPLE THICKNESS GATE DIELECTRICS FOR REPLACEMENT GATE FIELD EFFECT TRANSISTORS 有权
    用于更换栅极场效应晶体管的多个厚度栅极电介质

    公开(公告)号：US20150228747A1

    公开(公告)日：2015-08-13

    申请号：US14179074

    申请日：2014-02-12

    申请人： International Business Machines Corporation

    发明人： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Sean M. Polvino ,  Ravikumar Ramachandran ,  Shahab Siddiqui

    IPC分类号： H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423

    CPC分类号： H01L29/513 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

    摘要： After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.

    摘要翻译： 在去除一次性栅极结构以在平坦化介电层中形成栅极空腔之后，氧化硅层被共形沉积在栅极腔中的基于氧化硅的栅极电介质部分上。 氧化硅层的一部分可以被氮化以形成氮氧化硅层。 可以使用图案化的掩模材料层来物理地暴露半导体表面从第一类型的门腔。 可以除去氧化硅层，同时在第二型栅极腔中保留下面的基于氧化硅的栅极电介质部分。 在去除第二类型栅腔中的氧化硅层时，可以通过第三型栅极腔中的图案化掩模材料层来保护硅氮氧化物层和下面的基于氧化硅的栅极电介质的堆叠。 可以在栅极腔中形成高介电常数栅极电介质层，以提供不同类型的栅极电介质。