-
公开(公告)号：US07800402B1
公开(公告)日：2010-09-21
申请号：US11982865
申请日：2007-11-05
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778
摘要： A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.
摘要翻译： 可编程逻辑器件集成电路或其他集成电路可以具有产生数据信号的逻辑电路。 数据信号可以通过互连路由到其他逻辑电路。 互连可以是可编程的。 可以在每条互连线的末端使用电平恢复电路，以加强传输的数据信号。 连接到给定互连线的电平恢复电路可以产生在该互连线上的数据信号的真实和互补版本。 可以提供电平移位电路以升高互连上的数据信号。 每个互连线可以具有电平移位器电路，其接收数据信号的真实和互补版本并且产生数据信号的相应增强的真实和互补版本。 升压的信号可以提供给可编程查找表电路中的互补金属氧化物半导体晶体管栅极的控制输入。
-
公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
-
公开(公告)号：US20080169836A1
公开(公告)日：2008-07-17
申请号：US11653001
申请日：2007-01-12
IPC分类号： H03K19/094 , G11C5/02
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
-
公开(公告)号：US20100321984A1
公开(公告)日：2010-12-23
申请号：US12868575
申请日：2010-08-25
IPC分类号： G11C11/24
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
-
公开(公告)号：US09425192B2
公开(公告)日：2016-08-23
申请号：US12332928
申请日：2008-12-11
IPC分类号： H01L29/00 , H01L27/08 , H01L23/522 , H01L23/528
CPC分类号： H01L27/0805 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.
摘要翻译： 为集成电路提供电源去耦电容。 去耦电容器可以在电源电路组件之间分布成簇。 每个集群可以包含并联连接的多个单独的电容器单元。 每个电容器单元可以包含与电容器串联的电容器和电阻器。 电容器可以是金属 - 绝缘体 - 金属（MIM）电容器。 由于电介质缺陷，每个电池中的电阻可能会限制在电容器短路的情况下单个电容器的电流。
-
公开(公告)号：US08289755B1
公开(公告)日：2012-10-16
申请号：US12571346
申请日：2009-09-30
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.
摘要翻译： 提供了显示对软错误扰乱的抗扰度的内存元素。 存储器元件可以具有交叉耦合的反相器。 可以使用可编程施密特触发器来实现逆变器。 存储器元件可以通过向施密特触发器提供适当的电源电压来锁定和解锁。 存储元件可以各自具有形成双稳态元件，至少一个地址晶体管和至少一个写使能晶体管的四个逆变器状晶体管对。 写使能晶体管可以桥接四个节点中的两个。 存储元件可以通过打开和关闭写使能晶体管来锁定和解锁。 当存储器元件被解锁时，存储元件对状态变化的抵抗力较小，从而便于写操作。 当存储器元件被锁定时，存储元件可以表现出对软错误扰动的增强的抗扰性。
-
公开(公告)号：US07800400B2
公开(公告)日：2010-09-21
申请号：US11653001
申请日：2007-01-12
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
-
公开(公告)号：US20100148304A1
公开(公告)日：2010-06-17
申请号：US12332928
申请日：2008-12-11
IPC分类号： H01L29/00
CPC分类号： H01L27/0805 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.
摘要翻译： 为集成电路提供电源去耦电容。 去耦电容器可以在电源电路组件之间分布成簇。 每个集群可以包含并联连接的多个单独的电容器单元。 每个电容器单元可以包含与电容器串联的电容器和电阻器。 电容器可以是金属 - 绝缘体 - 金属（MIM）电容器。 由于电介质缺陷，每个电池中的电阻可能会限制在电容器短路的情况下单个电容器的电流。
-
9.发明授权Techniques for configuring programmable logic using on-chip nonvolatile memory 失效使用片上非易失性存储器配置可编程逻辑的技术公开(公告)号：US07710147B1
公开(公告)日：2010-05-04
申请号：US12122723
申请日：2008-05-19
IPC分类号： H03K19/173 , G06F9/00
CPC分类号： G06F17/5054 , H03K19/17764
摘要： Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.
摘要翻译： 技术和电路提供从片上非易失性存储器到可编程逻辑集成电路的可编程逻辑核心的快速，准确，适当和可靠的配置数据传输。 第一种技术包括不允许配置可编程逻辑，直到可以正确可靠地读取保持在片上非易失性存储器中的数据。 第二种技术包括验证在传送过程中配置数据是否从非易失性存储器传送到可编程逻辑核心，并且在传送过程中没有错误。 这两种技术可以在集成电路的配置期间单独组合或使用。
-
10.发明授权Techniques for configuring programmable logic using on-chip nonvolatile memory 失效使用片上非易失性存储器配置可编程逻辑的技术公开(公告)号：US07030647B1
公开(公告)日：2006-04-18
申请号：US10708478
申请日：2004-03-05
IPC分类号： G06F7/38
CPC分类号： G06F17/5054 , H03K19/17764
摘要： Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.
摘要翻译： 技术和电路提供从片上非易失性存储器到可编程逻辑集成电路的可编程逻辑核心的快速，准确，适当和可靠的配置数据传输。 第一种技术包括不允许配置可编程逻辑，直到可以正确可靠地读取保持在片上非易失性存储器中的数据。 第二种技术包括验证在传送过程中配置数据是否从非易失性存储器传送到可编程逻辑核心，并且在传送过程中没有错误。 这两种技术可以在集成电路的配置期间单独组合或使用。
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.021 秒)
