公开(公告)号：US20070063180A1

公开(公告)日：2007-03-22

申请号：US11516510

申请日：2006-09-07

申请人： Isamu Asano ,  Natsuki Sato ,  Kiyoshi Nakai

发明人： Isamu Asano ,  Natsuki Sato ,  Kiyoshi Nakai

IPC分类号： H01L29/04

CPC分类号： H01L27/2436 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

摘要： A non-volatile memory element includes a recording layer that includes a phase change material, a lower electrode provided in contact with the recording layer, an upper electrode provided in contact with a portion of the upper surface of the recording layer, a protective insulation film provided in contact with the other portion of the upper surface of the recording layer, and an interlayer insulation film provided on the protective insulation film. High thermal efficiency can thereby be obtained because the size of the area of contact between the recording layer and the upper electrode is reduced. Providing the protective insulation film between the interlayer insulation film and the upper surface of the recording layer makes it possible to reduce damage sustained by the recording layer during patterning of the recording layer or during formation of the through-hole for exposing a portion of the recording layer.

摘要翻译： 非易失性存储元件包括记录层，其包括相变材料，与记录层接触地设置的下电极，设置成与记录层的上表面的一部分接触的上电极，保护绝缘膜 设置成与记录层的上表面的另一部分接触，以及设置在保护绝缘膜上的层间绝缘膜。 由于记录层和上部电极之间的接触面积的尺寸减小，因此可获得高热效率。 在层间绝缘膜和记录层的上表面之间提供保护性绝缘膜使得可以减少在记录层的图案化期间或在用于曝光记录部分的通孔的形成期间记录层所承受的损伤 层。

公开(公告)号：US07508707B2

公开(公告)日：2009-03-24

申请号：US12003734

申请日：2007-12-31

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C14/00

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

摘要翻译： 公开了一种半导体存储装置，其中两种存储器，即易失性存储器和非易失性存储器安装在一个芯片上。 DRAM存储器阵列的数据在进入数据保持模式之前或在断电之前被保存在非易失性存储器的相应区域中，并且数据从非易失性存储器的区域传送到DRAM存储器阵列 数据保留模式或上电。 对DRAM存储器阵列进行正常读/写访问，而数据保留位于非易失性存储器的区域。

公开(公告)号：US20080130390A1

公开(公告)日：2008-06-05

申请号：US12003734

申请日：2007-12-31

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C7/08

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

公开(公告)号：US20060176724A1

公开(公告)日：2006-08-10

申请号：US11349959

申请日：2006-02-09

申请人： Isamu Asano ,  Yukio Fuji ,  Kiyoshi Nakai ,  Tsuyoshi Kawagoe

发明人： Isamu Asano ,  Yukio Fuji ,  Kiyoshi Nakai ,  Tsuyoshi Kawagoe

IPC分类号： G11C17/06

CPC分类号： G11C13/0004 ,  G11C13/003 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.

摘要翻译： 一种相变存储器件，包括相变存储器件; 半导体衬底; 设置在多个字线和以矩阵形式布置的多个位线的交点处的MOS晶体管; 多个相变存储元件，用于存储多个位的数据，各自形成在由相变材料制成的相变层中的与MOS晶体管的扩散层相反的上部区域上; 用于将多个相变存储元件中的每一个电连接到MOS晶体管的扩散层的下电极结构。

公开(公告)号：US07554147B2

公开(公告)日：2009-06-30

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L27/108

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

摘要翻译： 其中安装了DRAM和相变存储器（PCRAM）的存储器件具有形成在与DRAM位线共享的导电层上的DRAM位线，PCRAM位线或PCRAM源线，以及读出放大器 连接在DRAM位线和PCRAM位线之间。 存储器件还具有设置在DRAM位线的上层上的电容元件和设置在PCRAM位线的上层上的相变元件。 电容元件的下电极和相变存储元件的下电极形成在共用导电层上。

公开(公告)号：US07333363B2

公开(公告)日：2008-02-19

申请号：US11409088

申请日：2006-04-24

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C14/00

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

摘要翻译： 公开了一种半导体存储装置，其中两种存储器，即易失性存储器和非易失性存储器安装在一个芯片上。 DRAM存储器阵列的数据在进入数据保持模式之前或在断电之前被保存在非易失性存储器的相应区域中，并且数据从非易失性存储器的区域传送到DRAM存储器阵列 数据保留模式或上电。 对DRAM存储器阵列进行正常读/写访问，而数据保留位于非易失性存储器的区域。

公开(公告)号：US20060239097A1

公开(公告)日：2006-10-26

申请号：US11409088

申请日：2006-04-24

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C7/00

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

公开(公告)号：US20080043522A1

公开(公告)日：2008-02-21

申请号：US11666160

申请日：2005-10-25

申请人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

发明人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/78 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

摘要翻译： 为了通过获得用于高集成相变存储器件的足够的写入电流来提供有利于布局和操作控制的相变存储器件，本发明的非易失性半导体存储器件，其中字线和位线被布置成矩阵型， 形状包括形成在字线和位线的每个交叉点处的选择晶体管，以及多个存储元件，其一端共同连接到选择晶体管，并且在另一端连接到不同的元件选择线，并且能够 写和读数据。 通过提供预定电流通过选择晶体管并通过连接到所选择的存储元件的元件选择线来控制所选存储元件的写和读操作，并且元件选择线与位线并联布置。

公开(公告)号：US07502252B2

公开(公告)日：2009-03-10

申请号：US11666160

申请日：2005-10-25

申请人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

发明人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/78 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

摘要翻译： 为了通过获得用于高集成相变存储器件的足够的写入电流来提供有利于布局和操作控制的相变存储器件，本发明的非易失性半导体存储器件，其中字线和位线被布置成矩阵型， 形状包括形成在字线和位线的每个交叉点处的选择晶体管，以及多个存储元件，其一端共同连接到选择晶体管，并且在另一端连接到不同的元件选择线，并且能够 写和读数据。 通过提供预定电流通过选择晶体管并通过连接到所选择的存储元件的元件选择线来控制所选存储元件的写和读操作，并且元件选择线与位线并联布置。

公开(公告)号：US20060211231A1

公开(公告)日：2006-09-21

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L21/3205

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.