公开(公告)号：US20060211231A1

公开(公告)日：2006-09-21

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L21/3205

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

公开(公告)号：US07449711B2

公开(公告)日：2008-11-11

申请号：US11329224

申请日：2006-01-11

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

IPC分类号： H01L47/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

摘要翻译： 相变存储器件包括沿行方向延伸的多个位线，沿列方向延伸的多条选择线，以及各自设置在位线和选择线之间的交叉点之一处的存储单元阵列。 每个存储单元包括串联的硫族化物元件和二极管，以及二极管的n型层下面的n型接触层。 相邻的两个存储单元共享连接n型接触层和位线的公共位线接触插头。

公开(公告)号：US20060151771A1

公开(公告)日：2006-07-13

申请号：US11329224

申请日：2006-01-11

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Yukio Fuji ,  Kiyoshi Nakai ,  Kazuhiko Kajigaya

IPC分类号： H01L29/02

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

摘要翻译： 相变存储器件包括沿行方向延伸的多个位线，沿列方向延伸的多条选择线，以及各自设置在位线和选择线之间的交叉点之一处的存储单元阵列。 每个存储单元包括串联的硫族化物元件和二极管，以及二极管的n型层下面的n型接触层。 相邻的两个存储单元共享连接n型接触层和位线的公共位线接触插头。

公开(公告)号：US07554147B2

公开(公告)日：2009-06-30

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L27/108

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

摘要翻译： 其中安装了DRAM和相变存储器（PCRAM）的存储器件具有形成在与DRAM位线共享的导电层上的DRAM位线，PCRAM位线或PCRAM源线，以及读出放大器 连接在DRAM位线和PCRAM位线之间。 存储器件还具有设置在DRAM位线的上层上的电容元件和设置在PCRAM位线的上层上的相变元件。 电容元件的下电极和相变存储元件的下电极形成在共用导电层上。

公开(公告)号：US07508707B2

公开(公告)日：2009-03-24

申请号：US12003734

申请日：2007-12-31

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C14/00

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

摘要翻译： 公开了一种半导体存储装置，其中两种存储器，即易失性存储器和非易失性存储器安装在一个芯片上。 DRAM存储器阵列的数据在进入数据保持模式之前或在断电之前被保存在非易失性存储器的相应区域中，并且数据从非易失性存储器的区域传送到DRAM存储器阵列 数据保留模式或上电。 对DRAM存储器阵列进行正常读/写访问，而数据保留位于非易失性存储器的区域。

公开(公告)号：US20080130390A1

公开(公告)日：2008-06-05

申请号：US12003734

申请日：2007-12-31

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C7/08

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

公开(公告)号：US07333363B2

公开(公告)日：2008-02-19

申请号：US11409088

申请日：2006-04-24

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C14/00

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

摘要翻译： 公开了一种半导体存储装置，其中两种存储器，即易失性存储器和非易失性存储器安装在一个芯片上。 DRAM存储器阵列的数据在进入数据保持模式之前或在断电之前被保存在非易失性存储器的相应区域中，并且数据从非易失性存储器的区域传送到DRAM存储器阵列 数据保留模式或上电。 对DRAM存储器阵列进行正常读/写访问，而数据保留位于非易失性存储器的区域。

公开(公告)号：US20060239097A1

公开(公告)日：2006-10-26

申请号：US11409088

申请日：2006-04-24

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C7/00

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

公开(公告)号：US20060024875A1

公开(公告)日：2006-02-02

申请号：US11234118

申请日：2005-09-26

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US5981369A

公开(公告)日：1999-11-09

申请号：US865864

申请日：1997-05-30

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/823871 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/76849 ,  H01L21/76853 ,  H01L27/10855 ,  H01L27/10894

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在半导体基板上淀积5​​00℃以下的温度。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。