-
1.发明授权Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor 有权非易失性可重新编程的互连单元，具有可编程的埋入式源/漏极，在感应晶体管中
公开(公告)号：US6137728A
公开(公告)日：2000-10-24
申请号：US205678
申请日：1998-12-04
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11803 , G11C16/0441 , H01L27/115
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.
摘要翻译： 公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。 每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。 通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。 感测场效应晶体管的源极/漏极由在形成多晶硅浮置栅极和控制栅极之前形成的掩埋掺杂层（例如P掺杂衬底中的N +）形成。 掺杂剂从掩埋源/漏极到浮置栅极下方的沟道的横向扩散有助于在擦除和编程操作期间的电子隧穿，并且埋入源/分级结的接合点降低带对带隧穿泄漏。
-
2.发明授权Nonvolatile reprogrammable interconnect cell with programmable buried bitline 有权具有可编程掩埋位线的非易失性可编程互连单元
公开(公告)号：US6072720A
公开(公告)日：2000-06-06
申请号：US205876
申请日：1998-12-04
申请人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
发明人： Jack Zezhong Peng , Robert M. Salter, III , Volker Hecht , Kyung Joon Han , Robert U. Broze , Victor Levchenko
IPC分类号： G11C16/04 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/11524
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.
摘要翻译： 公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。 每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。 单元的编程通过与开关晶体管和感测晶体管并置的埋入位线来实现，开关晶体管和浮动栅极和控制栅极在其上。 感测晶体管可以与开关晶体管的制造同时制造，由此两个晶体管的掺杂剂浓度相同。
-
3.发明授权Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase 有权非易失性可编程互连单元，具有用于编程和擦除的FN隧穿装置公开(公告)号：US06252273B1
公开(公告)日：2001-06-26
申请号：US09138838
申请日：1998-08-24
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： A programmable interconnect cell for selectively connecting circuit nodes of a field programmable integrated circuit array in a semiconductor substrate includes a switch field effect transistor, a sense field effect transistor, and an electron tunneling device with the transistors and electron tunneling device having interconnected floating gates and interconnected control gates. The floating gates comprise a first polysilicon layer which is restricted to each cell, and the control gates comprise a second polysilicon layer which extends to adjacent cells in the row. The source/drain regions of the sense transistor extend to source/drain regions of sense amplifiers in adjacent rows. Programming and erasing of the switch transistor is effected entirely by electron tunneling in the electron tunneling device.
摘要翻译： 用于选择性地连接半导体衬底中的现场可编程集成电路阵列的电路节点的可编程互连单元包括开关场效应晶体管，感测场效应晶体管和电子隧穿装置，晶体管和电子隧穿装置具有互连的浮动栅极和 互连控制门。 浮置栅极包括限于每个单元的第一多晶硅层，并且控制栅极包括延伸到该行中的相邻单元的第二多晶硅层。 感测晶体管的源极/漏极区域延伸到相邻行中的读出放大器的源极/漏极区域。 开关晶体管的编程和擦除完全由电子隧穿装置中的电子隧穿实现。
-
4.发明授权
公开(公告)号：US5838040A
公开(公告)日：1998-11-17
申请号：US829374
申请日：1997-03-31
申请人： Robert M. Salter, III , Kyung Joon Han , Jack Zezhong Peng , Victor Levchenko , Robert V. Broze
发明人： Robert M. Salter, III , Kyung Joon Han , Jack Zezhong Peng , Victor Levchenko , Robert V. Broze
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/82 , H01L27/115 , H01L29/788 , H01L29/792 , H03K19/173
CPC分类号： G11C16/0441 , H01L27/115
摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.
摘要翻译： 公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。 每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是公共的，并且控制栅极是共同的。 通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。
-
公开(公告)号：US5773862A
公开(公告)日：1998-06-30
申请号：US704853
申请日：1996-08-27
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115 , H01L27/11524
摘要： The present invention provides for a programming portion of an FPGA cell of an integrated circuit and a process of manufacturing the programming portion. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors share a common N+ source/drain region, which is self-aligned with the gates of both transistors. With the select transistor separated from the EPROM transistor and the self-aligned common N+ region, the threshold voltage V.sub.T of the select transistor can be set precisely. This allows good control over the programming voltage for the control gate of the EPROM transistor and the time to program the floating gate of the EPROM transistor.
摘要翻译： 本发明提供了集成电路的FPGA单元的编程部分和制造编程部分的过程。 编程部分具有EPROM晶体管和分离的选择晶体管，选择晶体管的栅极连接到EPROM晶体管的控制栅极。 两个晶体管共享共同的N +源极/漏极区域，其与两个晶体管的栅极自对准。 利用从EPROM晶体管和自对准公共N +区域分离的选择晶体管，可以精确地设置选择晶体管的阈值电压VT。 这允许对EPROM晶体管的控制栅极的编程电压的良好控制以及对EPROM晶体管的浮置栅极进行编程的时间。
-
6.发明授权Programming method for non-volatile memory and non-volatile memory-based programmable logic device 有权非易失性存储器和非易失性存储器可编程逻辑器件的编程方法公开(公告)号：US07362610B1
公开(公告)日：2008-04-22
申请号：US11319751
申请日：2005-12-27
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.
摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。
-
7.发明授权Programming method for non-volatile memory and non-volatile memory-based programmable logic device 有权非易失性存储器和非易失性存储器可编程逻辑器件的编程方法公开(公告)号：US07623390B2
公开(公告)日：2009-11-24
申请号：US12024867
申请日：2008-02-01
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.
摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。
-
8.发明授权Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage 有权使用反向偏置电压擦除现场可编程门阵列的可编程互连单元的方法公开(公告)号：US07593268B2
公开(公告)日：2009-09-22
申请号：US11567625
申请日：2006-12-06
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , H03K19/17748 , H03K19/1776
摘要： A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.
摘要翻译： 一种用于擦除FPGA中的非易失性存储单元互连开关的方法，包括提供具有包含多个非易失性存储单元互连开关的核的FPGA，每个开关形成在开关阱区中并耦合到源/ 形成在与开关阱区域分离的接地阱区域中的n沟道晶体管的漏极。 选择非易失性存储单元互连开关进行擦除。 开关井区域与地面断开。 将VCC电位施加到开关阱区域和与其耦合的n沟道晶体管的漏极，并且将擦除电位施加到所选择的非易失性存储器单元互连开关的栅极。
-
公开(公告)号：US07573746B1
公开(公告)日：2009-08-11
申请号：US11861504
申请日：2007-09-26
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/04 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/3431 , G11C29/50 , H03K19/17776 , H03K19/1778
摘要： A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.
摘要翻译： 一种用于将数据存储在非易失性存储单元阵列的存储单元中的节点的方法，包括将非易失性存储单元阵列的非易失性设备设置为期望状态的步骤，将上拉设备和非易失性设备偏置 所述非易失性存储单元阵列的第一组行到关闭状态，将数据加载到所述非易失性存储单元阵列的列线上并且偏置所述非易失性存储单元阵列的存储单元中的第二组行中的非易失性设备， 非易失性存储单元阵列，用于存储来自非易失性存储单元阵列的存储单元中节点上列列的数据。
-
10.发明授权
公开(公告)号：US5606710A
公开(公告)日：1997-02-25
申请号：US359417
申请日：1994-12-20
申请人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
发明人： Christopher M. Hall , Gary D. Phillips , William E. Miller , David W. Weinrich , Robert M. Salter, III , Richard E. Crippen
CPC分类号： G11C16/102 , G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package. In other modes of operation, however, the signals input from (or output to) the feed-through package pads are re-routed by transfer gates to the non-volatile memory die.
摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 在非易失性存储器管芯上提供多个馈通以提供从处理器管芯到非易失性存储器管芯相对于处理器管芯的阴影中的封装焊盘的通信路径，从而防止从 处理器裸片到封装垫。 在正常运行模式下，这些焊盘专门用作馈通，提供处理器管芯上的特定焊盘与封装上的特定焊盘之间的直接连接。 然而，在其他操作模式中，从（或输出到）馈通封装焊盘输入的信号通过传输门被重新路由到非易失性存储器管芯。
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.028 秒)
