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1.发明授权Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase 有权非易失性可编程互连单元，具有用于编程和擦除的FN隧穿装置公开(公告)号：US06252273B1
公开(公告)日：2001-06-26
申请号：US09138838
申请日：1998-08-24
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： A programmable interconnect cell for selectively connecting circuit nodes of a field programmable integrated circuit array in a semiconductor substrate includes a switch field effect transistor, a sense field effect transistor, and an electron tunneling device with the transistors and electron tunneling device having interconnected floating gates and interconnected control gates. The floating gates comprise a first polysilicon layer which is restricted to each cell, and the control gates comprise a second polysilicon layer which extends to adjacent cells in the row. The source/drain regions of the sense transistor extend to source/drain regions of sense amplifiers in adjacent rows. Programming and erasing of the switch transistor is effected entirely by electron tunneling in the electron tunneling device.
摘要翻译： 用于选择性地连接半导体衬底中的现场可编程集成电路阵列的电路节点的可编程互连单元包括开关场效应晶体管，感测场效应晶体管和电子隧穿装置，晶体管和电子隧穿装置具有互连的浮动栅极和 互连控制门。 浮置栅极包括限于每个单元的第一多晶硅层，并且控制栅极包括延伸到该行中的相邻单元的第二多晶硅层。 感测晶体管的源极/漏极区域延伸到相邻行中的读出放大器的源极/漏极区域。 开关晶体管的编程和擦除完全由电子隧穿装置中的电子隧穿实现。
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公开(公告)号：US5773862A
公开(公告)日：1998-06-30
申请号：US704853
申请日：1996-08-27
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115 , H01L27/11524
摘要： The present invention provides for a programming portion of an FPGA cell of an integrated circuit and a process of manufacturing the programming portion. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors share a common N+ source/drain region, which is self-aligned with the gates of both transistors. With the select transistor separated from the EPROM transistor and the self-aligned common N+ region, the threshold voltage V.sub.T of the select transistor can be set precisely. This allows good control over the programming voltage for the control gate of the EPROM transistor and the time to program the floating gate of the EPROM transistor.
摘要翻译： 本发明提供了集成电路的FPGA单元的编程部分和制造编程部分的过程。 编程部分具有EPROM晶体管和分离的选择晶体管，选择晶体管的栅极连接到EPROM晶体管的控制栅极。 两个晶体管共享共同的N +源极/漏极区域，其与两个晶体管的栅极自对准。 利用从EPROM晶体管和自对准公共N +区域分离的选择晶体管，可以精确地设置选择晶体管的阈值电压VT。 这允许对EPROM晶体管的控制栅极的编程电压的良好控制以及对EPROM晶体管的浮置栅极进行编程的时间。
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3.发明授权Technique to prevent deprogramming a floating gate transistor used to directly switch a large electrical signal 失效用于防止对用于直接切换大电信号的浮栅晶体去编程技术
公开(公告)号：US5457653A
公开(公告)日：1995-10-10
申请号：US270869
申请日：1994-07-05
申请人： Robert J. Lipp
发明人： Robert J. Lipp
CPC分类号： G11C16/3427 , G11C16/3418
摘要： A novel method of connecting and operating an NVM transistor in the switching circuit is provided. A full voltage signal can be switched across an NVM transistor. The device is turned on prior to the signal switching and the electrical characteristics of the NVM device relative to the associated circuitry is carefully regulated to prevent the source-drain voltage from rising above a preselected maximum voltage (e.g. 1 v). Two embodiments of the present invention are described. In the first embodiment, the relative impedances of the NVM transistor and its driving circuit are controlled. The driver circuit and the NVM transistor switch act as a resistor divider circuit with a percentage of the full switching voltage appearing across the NVM transistor and the driver circuit according to their relative impedances. The second embodiment is applicable when the NVM transistor switch drives a capacitive load. The rise time of the signal to be switched is controlled. This can be done by controlling the driver circuit turn-on time, the relative resistor-capacitor (RC) risetime on either side of the NVM switch, or a combination of the two techniques. If the risetime of the switching signal is slow enough, the voltage at the output terminal of the NVM transistor closely follows the input voltage to minimize the source-drain voltage.
摘要翻译： 提供了一种在开关电路中连接和操作NVM晶体管的新颖方法。 可以在NVM晶体管上切换全电压信号。 该器件在信号切换之前被接通，并且NVM器件相对于相关电路的电特性被小心地调节以防止源极 - 漏极电压升高到高于预选的最大电压（例如1v）。 对本发明的两个实施例进行说明。 在第一实施例中，控制NVM晶体管及其驱动电路的相对阻抗。 驱动电路和NVM晶体管开关作为电阻分压电路，其全开关电压的百分比根据其相对阻抗出现在NVM晶体管和驱动电路两端。 当NVM晶体管开关驱动电容性负载时，第二实施例是可应用的。 控制要切换的信号的上升时间。 这可以通过控制驱动电路接通时间，NVM开关两侧的相对电阻 - 电容（RC）上升时间，或两种技术的组合来完成。 如果开关信号的上升时间足够慢，则NVM晶体管的输出端子处的电压紧跟输入电压，以使源极 - 漏极电压最小化。
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公开(公告)号：US4165642A
公开(公告)日：1979-08-28
申请号：US889492
申请日：1978-03-22
申请人： Robert J. Lipp
发明人： Robert J. Lipp
CPC分类号： H01L27/0716 , G01K1/028 , G01K7/01
摘要： A monolithic integrated complementary metal oxide semiconductor (CMOS) circuit senses internal junction temperature and converts it to a binary coded decimal output signal. The circuit compares a temperature dependent junction voltage with a bandgap reference voltage controlled by a very stable amplifier. The comparison differential is then converted to a binary coded decimal output signal by an analog to digital converter. The circuit utilizes parasitic bipolar NPN transistor elements formed from a substrate of the chip in a conventional CMOS fabrication process. The principles of the present invention are also broadly applicable to other semiconductor technologies such as integrated injection logic (I.sup.2 L).
摘要翻译： 单片集成互补金属氧化物半导体（CMOS）电路感测内部结温，并将其转换为二进制编码十进制输出信号。 该电路将温度依赖结电压与由非常稳定的放大器控制的带隙参考电压进行比较。 然后，比较差分由模数转换器转换为二进制编码的十进制输出信号。 该电路利用在常规CMOS制造工艺中由芯片的衬底形成的寄生双极型NPN晶体管元件。 本发明的原理也广泛地适用于诸如集成注入逻辑（I2L）的其它半导体技术。
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公开(公告)号：US20190269041A1
公开(公告)日：2019-08-29
申请号：US16399729
申请日：2019-04-30
申请人： Robert J. Lipp , Phillip N. Hughes
发明人： Robert J. Lipp , Phillip N. Hughes
摘要： A cold plate compatible with the Open Compute Project Rack specification is disclosed. The cold plate is mounted in a compatible rack with removable trays mounted on support and coupling rails affixed to the underside of the cold plate thus supporting the trays during insertion and operation.
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6.发明授权Multicast packet duplication at random node or at egress port with frame synchronization 失效在帧同步的随机节点或出口端口进行组播数据包复制公开(公告)号：US06751219B1
公开(公告)日：2004-06-15
申请号：US09553500
申请日：2000-04-20
申请人： Robert J. Lipp , Younes Boura
发明人： Robert J. Lipp , Younes Boura
IPC分类号： H04J1500
CPC分类号： H04L49/201 , H04J3/0623 , H04J3/1617 , H04J2203/0019 , H04J2203/0023 , H04J2203/008 , H04L49/252 , H04Q11/0005 , H04Q2011/0047
摘要： Multicast is performed in a packet-based network switch having a switch fabric of store-and-forward switch nodes. Congestion and blocking at an ingress port is avoided because packet replication is performed at random nodes dispersed throughout the switch fabric. Each multicast packet inserted into the switch fabric by the ingress port is sent to a randomly-selected node. The random node replicates the multicast packet into many unicast packets that are routed to egress ports. A SONET frame can be divided into several multicast packets that are dispersed to different random nodes before replication, thus dispersing congestion. Replication can be delayed until the next SONET frame to prevent latency build up from propagation delays in the switch fabric. Alternately, the SONET payload envelope pointer can be advanced by the propagation delay. Lookup tables at the random nodes can include a list of destinations so that all the destination addresses do not have to be stored in each multicast packet header.
摘要翻译： 组播在具有存储转发交换机节点的交换结构的基于分组的网络交换机中执行。 避免入口端口的拥塞和阻塞，因为在整个交换结构中分散的随机节点执行分组复制。 由入口端口插入交换机结构的每个组播数据包都将发送到随机选择的节点。 随机节点将组播数据包复制到路由到出口端口的许多单播数据包中。 SONET帧可以分为几个组播数据包，在复制之前分散到不同的随机节点，从而分散拥塞。 可以将复制延迟到下一个SONET帧，以防止交换结构中的传播延迟产生延迟。 或者，SONET有效载荷包络指针可以通过传播延迟来提前。 随机节点处的查找表可以包括目的地列表，使得所有目的地址不必被存储在每个多播包头中。
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公开(公告)号：US5764096A
公开(公告)日：1998-06-09
申请号：US754116
申请日：1996-11-21
IPC分类号： G11C16/04 , H03K19/173 , G11C11/34
CPC分类号： H03K19/1736 , G11C16/0441
摘要： A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.
摘要翻译： 一个可编程互连，将独立的开关晶体管与独立的NVM编程和擦除元件紧密集成。 编程元件是EPROM晶体管，擦除元件是Fowler-Nordheim隧穿器件。 一个单一的浮动栅极由开关晶体管和NVM编程和对浮动栅极充电和放电的元件共享。 共享浮栅结构是集成可编程互连的存储器结构，并控制开关晶体管的阻抗。
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公开(公告)号：US5367210A
公开(公告)日：1994-11-22
申请号：US836048
申请日：1992-02-12
申请人： Robert J. Lipp
发明人： Robert J. Lipp
IPC分类号： H03K17/00 , H03K17/16 , H03K19/00 , H03K19/003 , H03K19/092
CPC分类号： H03K19/0013 , H03K17/163 , H03K19/00361 , H03K2217/0036
摘要： An output buffer and a method provide controlled low noise operation using a current mirror which provides a rapid increase in the gate voltage of an output transistor prior to the gate voltage reaching the threshold voltage of the output transistor and provide a constant current voltage ramp thereafter. In one embodiment, the present invention automatically compensates for normal variations in transistor channel length due to fluctuations of process parameters. In one embodiment, a mechanism for switching off the current mirror is provided to reduce power consumption.
摘要翻译： 输出缓冲器和方法使用电流镜提供受控的低噪声操作，其在栅极电压达到输出晶体管的阈值电压之前提供输出晶体管的栅极电压的快速增加，此后提供恒定的电流电压斜坡。 在一个实施例中，由于工艺参数的波动，本发明自动补偿晶体管沟道长度的正常变化。 在一个实施例中，提供用于关闭电流镜的机构以减少功耗。
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9.发明授权Apparatus for heating and controlling temperature in an integrated circuit chip 失效用于加热和控制集成电路芯片中的温度的装置
公开(公告)号：US5309090A
公开(公告)日：1994-05-03
申请号：US579770
申请日：1990-09-06
申请人： Robert J. Lipp
发明人： Robert J. Lipp
CPC分类号： G01R31/2877 , G01R31/2856 , G01R31/2891
摘要： A method and an apparatus to heat an integrated circuit and regulate its temperature for the purposes of burn-in and temperature testing are provided. The circuit is heated internally by integrating a heating means. Sensing and controlling means may also be integrated. Such heating and controlling are activated by external signals applied to the IC. Practical means to heat the integrated circuit with pre-existing components is provided.
摘要翻译： 提供了一种用于加热集成电路并调节其温度以便进行老化和温度测试的方法和装置。 通过集成加热装置将电路内部加热。 感测和控制装置也可以被集成。 这种加热和控制由施加到IC的外部信号激活。 提供了使用预先存在的组件加热集成电路的实际手段。
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10.发明授权Method for operating a linear feedback shift register as a serial shift register with a crosscheck grid structure 失效将线性反馈移位寄存器作为具有交叉检查网格结构的串行移位寄存器的方法
公开(公告)号：US4975640A
公开(公告)日：1990-12-04
申请号：US482458
申请日：1990-02-20
申请人： Robert J. Lipp
发明人： Robert J. Lipp
摘要： A method for operating a multiple input linear feedback shift register (LFSR) as a conventional shift register so that input multiplexers can be eliminated on each parallel input when associated with a CrossCheck matrix. A linear feedback shift register coupled through sense lines of a CrossCheck test matrix is operated as a serial shift register by inputting serial data at the serial data input while maintaining parallel input lines at a zero logic level. Further, zero logic level serial data (null data) is input serially through the shift register prior to the enabling of the parallel input. The method significantly reduces the number of logic structures required to shift the data out serially.
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