公开(公告)号：US10536303B1

公开(公告)日：2020-01-14

申请号：US16203101

申请日：2018-11-28

申请人： Jacob Pike ,  Mahdi Parvizi ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

发明人： Jacob Pike ,  Mahdi Parvizi ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

IPC分类号： H04L25/03 ,  H03K3/356

摘要： A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary ½-rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by ¼-rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any ½-rate clock. In some implementations, every switch of at least one of the taps is driven by one of the ¼-rate clocks.

公开(公告)号：US10554453B1

公开(公告)日：2020-02-04

申请号：US16379502

申请日：2019-04-09

申请人： Mahdi Parvizi ,  Jacob Pike ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

发明人： Mahdi Parvizi ,  Jacob Pike ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H03K3/356

摘要： A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

公开(公告)号：US09787466B2

公开(公告)日：2017-10-10

申请号：US15064975

申请日：2016-03-09

申请人： Sadok Aouini ,  Naim Ben-Hamida ,  Mahdi Parvizi

发明人： Sadok Aouini ,  Naim Ben-Hamida ,  Mahdi Parvizi

IPC分类号： H03D3/24 ,  H04L7/033 ,  H03L7/099 ,  H03L7/085 ,  H03L7/08 ,  H03L7/23 ,  H03L7/07 ,  H03L7/06 ,  H03L7/193 ,  H03L7/18 ,  H03L7/197 ,  H03L7/093

CPC分类号： H04L7/0331 ,  H03L7/06 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/1806 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/06 ,  H03L2207/50

摘要： A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

公开(公告)号：US20170264425A1

公开(公告)日：2017-09-14

申请号：US15064975

申请日：2016-03-09

申请人： Sadok Aouini ,  Naim Ben-Hamida ,  Mahdi Parvizi

发明人： Sadok Aouini ,  Naim Ben-Hamida ,  Mahdi Parvizi

IPC分类号： H04L7/033

CPC分类号： H04L7/0331 ,  H03L7/06 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/1806 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/06 ,  H03L2207/50

摘要： A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.