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8 条记录 (耗时 0.012 秒)

    Quarter-rate charge-steering decision feedback equalizer (DFE) taps
    1.
    发明授权
    Quarter-rate charge-steering decision feedback equalizer (DFE) taps 有权

    公开(公告)号：US10536303B1

    公开(公告)日：2020-01-14

    申请号：US16203101

    申请日：2018-11-28

    申请人： Jacob Pike ,  Mahdi Parvizi ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

    发明人： Jacob Pike ,  Mahdi Parvizi ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

    IPC分类号： H04L25/03 ,  H03K3/356

    摘要： A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary ½-rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by ¼-rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any ½-rate clock. In some implementations, every switch of at least one of the taps is driven by one of the ¼-rate clocks.

    Method and system for phase and byte alignment on a multiplexed high speed bus
    2.
    发明授权
    Method and system for phase and byte alignment on a multiplexed high speed bus 失效
    多路复用高速总线上相位和字节对齐的方法和系统

    公开(公告)号：US07742507B1

    公开(公告)日：2010-06-22

    申请号：US11391537

    申请日：2006-03-28

    申请人： Christopher W. Kurowski ,  Naim Ben-Hamida

    发明人： Christopher W. Kurowski ,  Naim Ben-Hamida

    IPC分类号： H04J3/02

    CPC分类号： H04J3/047 ,  H03K5/135

    摘要： A method and system for multiplexing a plurality of serialized data signals in which a first integrated circuit device generates a plurality of serialized data signals. A second integrated circuit device is in electrical communication with the first integrated circuit device. The second integrated circuit device includes a multiplexer operable to generate a multiplexed output signal from the plurality of serialized data signals received from the first integrated circuit. A phase data and byte snapshot back channel is transmitted from the second integrated circuit device to the first integrated circuit device. The phase data and byte snapshot back channel carries phase data and periodic snapshots of the serialized data signals. The phase data and byte snapshot back channel is used by the first integrated circuit device to adjust the phase of each of the plurality of serialized data signals to preserve bit and byte alignment. Such a method and system can be implemented as a 4×10 Gbit/Sec. system that is multiplexed to a 40 Gbit/Sec. stream as may be used in optical transmission systems.

    摘要翻译： 一种用于多路复用多个串行数据信号的方法和系统，其中第一集成电路器件产生多个串行数据信号。 第二集成电路装置与第一集成电路装置电连通。 第二集成电路装置包括多路复用器，可操作以从多个从第一集成电路接收的串行化数据信号产生多路复用的输出信号。 相位数据和字节快照反向通道从第二集成电路器件发送到第一集成电路器件。 相位数据和字节快照反向通道携带串行数据信号的相位数据和周期性快照。 相位数据和字节快照反向通道由第一集成电路器件用于调整多个串行数据信号中的每一个的相位以保持位和字节对齐。 这种方法和系统可以实现为4×10 Gbit / Sec。 系统被复用到40 Gbit / Sec。 流可以用于光传输系统。

    Digital-to-analog converter and generation of high-bandwidth analog signals
    5.
    发明授权
    Digital-to-analog converter and generation of high-bandwidth analog signals 有权

    公开(公告)号：US10374623B1

    公开(公告)日：2019-08-06

    申请号：US16004673

    申请日：2018-06-11

    申请人： Shahab Oveis Gharan ,  Yuriy Greshishchev ,  Naim Ben-Hamida ,  Kim B. Roberts

    发明人： Shahab Oveis Gharan ,  Yuriy Greshishchev ,  Naim Ben-Hamida ,  Kim B. Roberts

    IPC分类号： H04B10/532 ,  H03M1/08 ,  H04Q11/00

    摘要： A controlled switch having N inputs and a single output (N≥2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields the high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.

    Quarter-rate charge-steering decision feedback equalizer (DFE)
    6.
    发明授权
    Quarter-rate charge-steering decision feedback equalizer (DFE) 有权

    公开(公告)号：US10554453B1

    公开(公告)日：2020-02-04

    申请号：US16379502

    申请日：2019-04-09

    申请人： Mahdi Parvizi ,  Jacob Pike ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

    发明人： Mahdi Parvizi ,  Jacob Pike ,  Naim Ben-Hamida ,  Sadok Aouini ,  Calvin Plett

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H03K3/356

    摘要： A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

    Method and system for phase and byte alignment on a multiplexed high speed bus
    8.
    发明授权
    Method and system for phase and byte alignment on a multiplexed high speed bus 失效
    多路复用高速总线上相位和字节对齐的方法和系统

    公开(公告)号：US08451870B1

    公开(公告)日：2013-05-28

    申请号：US12786826

    申请日：2010-05-25

    申请人： Christopher W. Kurowski ,  Naim Ben-Hamida

    发明人： Christopher W. Kurowski ,  Naim Ben-Hamida

    IPC分类号： H04J3/02

    CPC分类号： H04J3/047 ,  H03K5/135

    摘要： A method and system for multiplexing data signals is provided. A first circuit is operable to generate a plurality of serialized data signals and is operable to adjust a phase of at least one of the serialized data signals to adjust bit and byte alignment. A second circuit is coupled to the first circuit to receive the plurality of serialized data signals from the first circuit. The second circuit has a multiplexer operable to generate a multiplexed output signal from the received serialized data signals. The first circuit is further coupled to the second circuit by a back channel operable to carry information regarding bit alignment and byte alignment of the received serialized data signals.

    摘要翻译： 提供了一种用于复用数据信号的方法和系统。 第一电路可操作以产生多个串行数据信号，并且可操作以调整串行化数据信号中的至少一个的相位以调整位和字节对准。 第二电路耦合到第一电路以从第一电路接收多个串行数据信号。 第二电路具有多路复用器，用于从接收的串行数据信号产生多路复用的输出信号。 第一电路还通过可操作以携带关于接收的串行数据信号的位对齐和字节对准的信息的​​后向通道耦合到第二电路。