公开(公告)号：US08981841B2

公开(公告)日：2015-03-17

申请号：US13236970

申请日：2011-09-20

申请人： Jae-Bum Ko ,  Jong-Chern Lee ,  Sang-Jin Byeon

发明人： Jae-Bum Ko ,  Jong-Chern Lee ,  Sang-Jin Byeon

IPC分类号： H01L25/00 ,  G11C8/12

CPC分类号： G11C8/12

摘要： A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

摘要翻译： 半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号 以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

公开(公告)号：US20120249229A1

公开(公告)日：2012-10-04

申请号：US13236970

申请日：2011-09-20

申请人： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

发明人： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

IPC分类号： H01L25/00

CPC分类号： G11C8/12

摘要： A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

摘要翻译： 半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号 以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

公开(公告)号：US20120007624A1

公开(公告)日：2012-01-12

申请号：US12914424

申请日：2010-10-28

申请人： Sang-Jin Byeon ,  Jong-Chern Lee

发明人： Sang-Jin Byeon ,  Jong-Chern Lee

IPC分类号： G01R31/26

CPC分类号： G11C11/4072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C16/20

摘要： A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

摘要翻译： 用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。 第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。 通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据 比较结果。

公开(公告)号：US08760181B2

公开(公告)日：2014-06-24

申请号：US12914424

申请日：2010-10-28

申请人： Sang-Jin Byeon ,  Jong-Chern Lee

发明人： Sang-Jin Byeon ,  Jong-Chern Lee

IPC分类号： G01R31/36 ,  G11C5/02

CPC分类号： G11C11/4072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C16/20

摘要： A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

摘要翻译： 用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。 第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。 通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据 比较结果。

公开(公告)号：US08350362B2

公开(公告)日：2013-01-08

申请号：US12831341

申请日：2010-07-07

申请人： Sang-Jin Byeon ,  Jun-Gi Choi

发明人： Sang-Jin Byeon ,  Jun-Gi Choi

IPC分类号： H01L29/40

CPC分类号： H01L21/76879 ,  H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

摘要翻译： 半导体集成电路包括：半导体芯片; 通过芯片穿过设置在半导体芯片中的导电图案并切割导电图案; 以及设置在贯通芯片通孔的外周面上的绝缘图案，以使导电图案与贯通芯片通孔绝缘。

公开(公告)号：US08274856B2

公开(公告)日：2012-09-25

申请号：US12165057

申请日：2008-06-30

申请人： Sang-Jin Byeon

发明人： Sang-Jin Byeon

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

摘要翻译： 提供一种半导体器件，其包括内部电压发生器电路，其根据操作速度提供具有不同电平的内部电压。 半导体器件包括内部电压发生器电路，其被配置为接收操作速度信息以根据操作速度产生具有不同电平的内部电压; 以及使用内部电压工作的内部电路。

公开(公告)号：US07907462B2

公开(公告)日：2011-03-15

申请号：US12005506

申请日：2007-12-26

申请人： Sang-Jin Byeon

发明人： Sang-Jin Byeon

IPC分类号： G11C7/04 ,  G11C5/14

CPC分类号： G11C7/04 ,  G11C5/147 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4091

摘要： A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.

公开(公告)号：US07889574B2

公开(公告)日：2011-02-15

申请号：US12219572

申请日：2008-07-24

申请人： Sang-Jin Byeon ,  Kang-Seol Lee

发明人： Sang-Jin Byeon ,  Kang-Seol Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/12 ,  G11C7/06

摘要： A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.

摘要翻译： 半导体存储器件采用夹具来防止闩锁。 为此，半导体存储器件包括用于对一对位线进行预充电和均衡的预充电/均衡单元，以及用于产生控制预充电/均衡单元的使能和禁能的控制信号的控制信号产生单元，其中控制 信号发生单元包括钳位单元，用于将其源极电压钳位到低于其体积偏压的电压电平。

公开(公告)号：US07545203B2

公开(公告)日：2009-06-09

申请号：US11526818

申请日：2006-09-26

申请人： Sang-Jin Byeon ,  Seok-Cheol Yoon

发明人： Sang-Jin Byeon ,  Seok-Cheol Yoon

IPC分类号： G05F1/46 ,  H02M3/07

CPC分类号： G11C5/145

摘要： An inter voltage generation circuit includes a pumping voltage generator to generate a pumping voltage, a level comparator to compare the pumping voltage level with a peripheral voltage level and output an enable signal depending on the comparison result, and a peripheral voltage generator to output a pumping enable signal according to the enable signal and generate a peripheral voltage according to the enable signal.

摘要翻译： 电压产生电路包括产生泵浦电压的泵浦电压发生器，用于将泵浦电压电平与外围电压电平进行比较的电平比较器，并根据比较结果输出使能信号;以及外围电压发生器，输出泵浦 根据使能信号使能信号，并根据使能信号产生外设电压。

公开(公告)号：US07420358B2

公开(公告)日：2008-09-02

申请号：US11319299

申请日：2005-12-27

申请人： Sang-Jin Byeon ,  Seok-Cheol Yoon

发明人： Sang-Jin Byeon ,  Seok-Cheol Yoon

IPC分类号： G05F3/16 ,  G05F1/10

CPC分类号： G05F3/30

摘要： An internal voltage generating apparatus adaptive to a temperature change includes a reference voltage circuit including a complementary to absolute temperature (CTAT) type transistor and a proportional to absolute temperature (PTAT) type transistor for generating a first to a third initial reference voltage signals. A buffer circuit for buffering a first, a second and a third initial reference voltage signal is included to generate a first, a second, and a third reference voltage signal in response to enable signals. An internal voltage generating circuit is included to generate an internal voltage signal based on the first, the second and the third reference voltage signal by using an inputted power voltage.

摘要翻译： 适于温度变化的内部电压发生装置包括包括与绝对温度（CTAT）型晶体管互补的参考电压电路和用于产生第一至第三初始参考电压信号的绝对温度（PTAT）型晶体管的比例。 包括用于缓冲第一，第二和第三初始参考电压信号的缓冲电路，以响应于使能信号产生第一，第二和第三参考电压信号。 包括内部电压产生电路，以通过使用输入的电源电压来产生基于第一，第二和第三参考电压信号的内部电压信号。