公开(公告)号：US20110062508A1

公开(公告)日：2011-03-17

申请号：US12882436

申请日：2010-09-15

Applicant: Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

Inventor： Yoonmoon PARK ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

IPC: H01L29/788

CPC classification number: H01L27/11531 ,  H01L27/11526 ,  H01L28/20 ,  H01L28/24

Abstract: Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

Abstract translation: 提供了包括电阻器的半导体器件及其制造方法的实施例。 半导体器件包括设置在半导体衬底上以限定沟槽的模具图案，包括主体区域和第一和第二接触区域的电阻图案，其中主体区域覆盖沟槽的底部和侧壁，第一和第二接触区域 分别从模具图案的上表面上的身体区域延伸出来; 以及分别与第一和第二接触区域接触的第一和第二线路。

公开(公告)号：US20140151777A1

公开(公告)日：2014-06-05

申请号：US14096195

申请日：2013-12-04

Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

IPC: H01L29/788

CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

Abstract: Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

Abstract translation: 提供一种半导体存储器件及其制造方法，半导体存储器件可以包括半导体衬底，该半导体衬底具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，栅极 电极，设置在第一区域上以与有源区交叉，设置在栅电极和有源区之间的电荷存储图案，设置在栅电极和电荷存储图案之间并在第一沟槽上延伸以限定第一 第一沟槽中的空气间隙，以及设置成与第二沟槽的底表面间隔开的绝缘图案，以在第二沟槽中限定第二气隙。

公开(公告)号：US09041088B2

公开(公告)日：2015-05-26

申请号：US14339762

申请日：2014-07-24

Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/788 ,  H01L27/115 ,  H01L21/762

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。

公开(公告)号：US20150054176A1

公开(公告)日：2015-02-26

申请号：US14503498

申请日：2014-10-01

Applicant: Jae-Hwang Sim ,  Jinhyun Shin

Inventor： Jae-Hwang Sim ,  Jinhyun Shin

IPC: H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11531

Abstract: Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.

Abstract translation: 提供制造半导体器件的方法包括执行两个光刻工艺和两个间隔工艺，使得图案形成为具有小于光刻工艺限制的间距。 此外，通过执行一次光刻工艺同时限定线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。 还提供了相关设备。

公开(公告)号：US08772855B2

公开(公告)日：2014-07-08

申请号：US12882436

申请日：2010-09-15

Applicant: Yoonmoon Park ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

Inventor： Yoonmoon Park ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

IPC: H01L29/788

CPC classification number: H01L27/11531 ,  H01L27/11526 ,  H01L28/20 ,  H01L28/24

Abstract: Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

Abstract translation: 提供了包括电阻器的半导体器件及其制造方法的实施例。 半导体器件包括设置在半导体衬底上以限定沟槽的模具图案，包括主体区域和第一和第二接触区域的电阻图案，其中主体区域覆盖沟槽的底部和侧壁，第一和第二接触区域 分别从模具图案的上表面上的身体区域延伸出来; 以及分别与第一和第二接触区域接触的第一和第二线路。

公开(公告)号：US09166012B2

公开(公告)日：2015-10-20

申请号：US14096195

申请日：2013-12-04

Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/764 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

Abstract: Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

Abstract translation: 提供一种半导体存储器件及其制造方法，半导体存储器件可以包括半导体衬底，该半导体衬底具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，栅极 电极，设置在第一区域上以与有源区交叉，设置在栅电极和有源区之间的电荷存储图案，设置在栅电极和电荷存储图案之间并在第一沟槽上延伸以限定第一 第一沟槽中的空气间隙，以及设置成与第二沟槽的底表面间隔开的绝缘图案，以在第二沟槽中限定第二气隙。

公开(公告)号：US20140332894A1

公开(公告)日：2014-11-13

申请号：US14339762

申请日：2014-07-24

Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L29/06 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。

公开(公告)号：US09117654B2

公开(公告)日：2015-08-25

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

IPC: H01L21/467 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L23/544 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

公开(公告)号：US20140191405A1

公开(公告)日：2014-07-10

申请号：US14208456

申请日：2014-03-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US08598710B2

公开(公告)日：2013-12-03

申请号：US12950347

申请日：2010-11-19

Applicant: Yoonmoon Park ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

Inventor： Yoonmoon Park ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

IPC: H01L23/48

CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿透芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。