公开(公告)号：US08563378B2

公开(公告)日：2013-10-22

申请号：US13238104

申请日：2011-09-21

申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

IPC分类号： H01L21/336

CPC分类号： H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

摘要翻译： 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

公开(公告)号：US20060097319A1

公开(公告)日：2006-05-11

申请号：US11197836

申请日：2005-08-05

申请人： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

发明人： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

IPC分类号： H01L27/01

CPC分类号： H01L21/8221 ,  H01L21/28525 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L29/785

摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.

摘要翻译： 提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。 所述方法包括在单晶半导体层上形成层间绝缘层。 形成单晶半导体插塞以穿透层间绝缘层。 使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。 结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。 也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。 单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。 通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

公开(公告)号：US07276421B2

公开(公告)日：2007-10-02

申请号：US11197836

申请日：2005-08-05

申请人： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

发明人： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

IPC分类号： H01L21/331

CPC分类号： H01L21/8221 ,  H01L21/28525 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L29/785

摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.

摘要翻译： 提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。 所述方法包括在单晶半导体层上形成层间绝缘层。 形成单晶半导体插塞以穿透层间绝缘层。 使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。 结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。 也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。 单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。 通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

公开(公告)号：US07276404B2

公开(公告)日：2007-10-02

申请号：US11589618

申请日：2006-10-30

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

公开(公告)号：US20070042554A1

公开(公告)日：2007-02-22

申请号：US11589618

申请日：2006-10-30

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L21/336

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和方法消除了由于具有垂直堆叠的上下栅极图案的SRAM单元的结构特性而产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

公开(公告)号：US07135746B2

公开(公告)日：2006-11-14

申请号：US11268138

申请日：2005-11-07

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

公开(公告)号：US20060097328A1

公开(公告)日：2006-05-11

申请号：US11268138

申请日：2005-11-07

申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

IPC分类号： H01L29/76

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和该方法消除了具有垂直堆叠的上和下栅极图案的SRAM单元的结构特性所产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

公开(公告)号：US20120009767A1

公开(公告)日：2012-01-12

申请号：US13236000

申请日：2011-09-19

申请人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

发明人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

IPC分类号： H01L21/20

CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

公开(公告)号：US20090233405A1

公开(公告)日：2009-09-17

申请号：US12474896

申请日：2009-05-29

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.

摘要翻译： 形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层 图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层 结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层 半导体衬底的整个表面 使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心 一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

公开(公告)号：US07554140B2

公开(公告)日：2009-06-30

申请号：US11651892

申请日：2007-01-10

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC分类号： H01L31/062

CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

摘要翻译： 提供了一种NAND型非易失性存储器件及其形成方法。 在该方法中，多个单元层层叠在半导体基板上。 用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。 此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。