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    Manufacturing semiconductor devices
    1.
    发明授权
    Manufacturing semiconductor devices 有权
    制造半导体器件

    公开(公告)号：US08563378B2

    公开(公告)日：2013-10-22

    申请号：US13238104

    申请日：2011-09-21

    申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

    发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

    摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

    摘要翻译： 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

    Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns
    2.
    发明授权
    Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns 有权
    具有穿透导电图案和层间绝缘图案的垂直结构的半导体器件

    公开(公告)号：US09209244B2

    公开(公告)日：2015-12-08

    申请号：US13717803

    申请日：2012-12-18

    申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

    发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

    IPC分类号： H01L29/06 ,  H01L27/02 ,  H01L27/115

    CPC分类号： H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

    摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

    摘要翻译： 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130168800A1

    公开(公告)日：2013-07-04

    申请号：US13717803

    申请日：2012-12-18

    申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

    发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

    摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

    摘要翻译： 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08222742B2

    公开(公告)日：2012-07-17

    申请号：US12457290

    申请日：2009-06-05

    申请人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

    发明人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

    IPC分类号： H01L23/48

    CPC分类号： H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

    摘要翻译： 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

    Semiconductor device
    6.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20090315187A1

    公开(公告)日：2009-12-24

    申请号：US12457290

    申请日：2009-06-05

    申请人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

    发明人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

    IPC分类号： H01L23/522

    CPC分类号： H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

    摘要翻译： 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

    Vertical type semiconductor devices
    7.
    发明授权
    Vertical type semiconductor devices 有权
    垂直型半导体器件

    公开(公告)号：US09306041B2

    公开(公告)日：2016-04-05

    申请号：US14156607

    申请日：2014-01-16

    申请人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    发明人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    IPC分类号： H01L29/66 ,  H01L29/792 ,  H01L27/115

    CPC分类号： H01L29/66833 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

    摘要： A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

    摘要翻译： 垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。 字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。 连接图案将相邻的第一和第二字线的对电连接在同一平面中。 该设备可以是非易失性存储设备或不同类型的设备。

    Methods of manufacturing a semiconductor device
    8.
    发明授权
    Methods of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09087861B2

    公开(公告)日：2015-07-21

    申请号：US14156781

    申请日：2014-01-16

    申请人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    发明人： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

    IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

    CPC分类号： H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

    摘要翻译： 制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘 部分堆叠结构以形成初步的阶梯状图案结构。 初步阶形形状图案结构具有阶梯形边缘部分。 形成与基板表面接触的柱结构。 部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。 第二开口部分切割下牺牲层的至少边缘部分。