摘要:
A Class-D amplifier system may include an input stage that includes an Nth order filter, where N>1. The input stage filters an input signal to provide a filtered output signal, an input of the input stage being configured to receive the input signal as a digital pulse-width-modulated (PWM) signal. A comparator provides a quantized output signal based on the filtered output signal. An output stage is connected between a first voltage rail and a second voltage rail. The output stage provides a switching output signal at an output that varies between the first voltage rail and the second voltage rail based on the quantized output signal. A feedback path connects the output of the output stage with the input of the input stage, such that the Nth order filter compensates for variations in at least one of the first voltage rail and the second voltage rail.
摘要:
An amplifier system in accordance with an aspect of the present invention comprises a switching amplifier that drives a load with a pulse-width modulated (PWM) output signal that varies between first and second rails based on a first control input signal, and a common mode supply that provides a switching signal that varies between third and fourth rails to maintain a common mode voltage of the load at a level that is between the first and second rails.
摘要:
The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the output of the first integrator is greater than the output of the second integrator. The outputs of the first and second integrators are directly compared by the comparator without the necessity of a summing amplifier.
摘要:
An antenna is provided. This antenna is contained within a package that is secured to an IC (which allows radiation to propagated away for a printed circuit board so as to reduce interference), and this antenna includes two loop antennas that are shorted to ground and that “overlap” and includes a “via wall.” With this configuration, circular polarization can be achieved by varying the relative phases of the input signals, and the “via wall” improves efficiency by reducing surface waves.
摘要:
There are a variety of duty cycle systems, such as low noise amplifiers or LNAs, that have a large time varying current consumption, and parasitic inductances and resistance (usually from bondwires in the package) that can significantly affect supply currents. Thus, to compensate for these parasitics, a boost circuit is provided that allows for current to be supplied from a separate supply using a feedforward scheme to perform active decoupling.
摘要:
A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold.
摘要:
A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold.
摘要:
A circuit is provided for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge. The circuit is operable to receive a reference signal and to output an output signal. The circuit includes an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion is arranged to receive the reference signal and is operable to output a divided reference signal. The feedback divider portion is arranged to receive the output signal and is operable to output a divided feedback signal. The phase detector portion is operable to output a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion is operable to output a tuning signal based on the phase detector signal. The voltage controlled oscillator portion is operable to output the output signal based on the tuning signal. The phase detector portion is further operable to change the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal, and further based on the control signal and a rising edge of a clock pulse.
摘要:
An apparatus is provided. A plurality of transceiver antennas are arranged to form a phased array, where each antenna include a differential transmit antenna and a differential receive antenna arranged in a first pattern. A plurality of transceivers are arranged in a second pattern that is substantially symmetrical, and each transceiver is associated with at least one of the transceiver antennas and includes a feed network. Each feed network has a power amplifier (PA), a first matching network that is coupled between the PA and its associated transmit antenna so as to translate the phase of each differential transmit signal, a low noise amplifier (LNA), and a second matching network that is coupled between the LNA and its associated receive antenna so as to translate the phase of each differential receive signal.
摘要:
An amplifier having an active and passive gain stage connect to a load for driving a load according to a system analog input. A first embodiment of the amplifier in accordance with the present invention includes a logic network connected between a comparator network and a switching system, wherein the comparator network connects to the passive gain stage. Specifically, the active gain stage may include an active filter connected to receive an analog or digital input and provide a difference between the analog or digital input and the feedback signal relative to the gain factor of a gain unit connected to the active filter. The passive gain stage includes a passive filter. The logic network generates at least one switching signal which controls the switching system that includes at least one switching device to selectively provide power to the load. An output signal from the switching system provides output for the amplifier and is fed back to the active gain stage. In another embodiment, the output is a two-level signal and the passive and active filters are second order low pass filters, where the gain factor is about 25 or more. In yet another embodiment, the gain factor is approximately 250. Moreover, the amplifier may include a digital delta-sigma modulator connected to supply a two level input.