公开(公告)号：US20100237394A1

公开(公告)日：2010-09-23

申请号：US12659735

申请日：2010-03-19

申请人： Jai-Kyun Park ,  Hyeong-Sun Hong ,  Jong-Seop Lee ,  Yong-Il Kim ,  Yun-Sung Lee ,  Nam-Jung Kang ,  Jae-Hoon Song ,  Gil-Sub Kim

发明人： Jai-Kyun Park ,  Hyeong-Sun Hong ,  Jong-Seop Lee ,  Yong-Il Kim ,  Yun-Sung Lee ,  Nam-Jung Kang ,  Jae-Hoon Song ,  Gil-Sub Kim

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/10855

摘要： A semiconductor memory device includes unit active regions, word lines extending in a first direction over the unit active region, bit lines extending on the word lines in a second direction substantially perpendicularly to the first direction, first pad contacts in contact with central portions of the unit active regions, the first pad contacts being arranged between the word lines, direct contacts electrically connected between the first pad contacts and the bit lines, second pad contacts in contact with edge portions of the unit active regions, the second pad contacts being arranged between the word lines and between the bit lines, buried contacts electrically connected to the second pad contacts, and capacitors electrically connected to the buried contacts.

摘要翻译： 半导体存储器件包括单元有源区域，在单元有源区域上沿第一方向延伸的字线，沿着基本垂直于第一方向的第二方向在字线上延伸的位线，与第一方向的中心部分接触的第一焊盘触点 所述第一焊盘触点布置在所述字线之间，直接触点电连接在所述第一焊盘触点和所述位线之间，所述第二焊盘触点与所述单元有源区域的边缘部分接触，所述第二焊盘触点布置在 字线和位线之间，电连接到第二焊盘触点的埋入触点，以及电连接到埋入触点的电容器。

公开(公告)号：US20080284029A1

公开(公告)日：2008-11-20

申请号：US12151997

申请日：2008-05-12

申请人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

发明人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L29/4236 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876

摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.

摘要翻译： 在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。 在半导体衬底上形成第一层间电介质层。 形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。 位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。 在包括位线结构的半导体衬底上形成第二层间电介质层。 阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。 掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。 使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

公开(公告)号：US08378497B2

公开(公告)日：2013-02-19

申请号：US12758946

申请日：2010-04-13

申请人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

发明人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/4236 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876

摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.

摘要翻译： 在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。 在半导体衬底上形成第一层间电介质层。 形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。 位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。 在包括位线结构的半导体衬底上形成第二层间电介质层。 阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。 掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。 使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

公开(公告)号：US20100193966A1

公开(公告)日：2010-08-05

申请号：US12758946

申请日：2010-04-13

申请人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

发明人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

IPC分类号： H01L23/538

CPC分类号： H01L29/4236 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876

摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are is etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.

摘要翻译： 在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。 在半导体衬底上形成第一层间电介质层。 形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。 位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。 在包括位线结构的半导体衬底上形成第二层间电介质层。 阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。 掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。 使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成掩埋的接触孔，并且在埋入的接触孔中形成掩埋的接触塞。

公开(公告)号：US20080283957A1

公开(公告)日：2008-11-20

申请号：US12112438

申请日：2008-04-30

申请人： Nam-Jung Kang ,  Dong-Soo Woo ,  Hyeong-Sun Hong ,  Dong-Hyun Kim

发明人： Nam-Jung Kang ,  Dong-Soo Woo ,  Hyeong-Sun Hong ,  Dong-Hyun Kim

IPC分类号： H01L29/00 ,  H01L21/4763

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10855

摘要： Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.

摘要翻译： 提供制造具有自对准接触插头的半导体器件的方法。 方法包括在半导体衬底上形成下绝缘层，在下绝缘层上形成彼此平行的多个互连图案; 形成上部绝缘层，其被构造成填充在所述互连图案之间，并且形成与所述多个互连图案交叉的多个第一掩模图案，所述多个第一掩模图案中的所述第一掩模图案在具有所述上绝缘体的半导体衬底上彼此平行 层。 方法可以包括形成第二掩模图案，该第二掩模图案与多个第一掩模图案自对准，并且位于多个第一掩模图案之间，使用第一和第二掩模图案蚀刻上绝缘层和下绝缘层 以及所述多个互连图案作为蚀刻掩模，以形成暴露所述半导体衬底的多个接触孔，以及在所述多个接触孔中的相应接触孔中形成多个接触插塞。 还提供了半导体器件。

公开(公告)号：US07777265B2

公开(公告)日：2010-08-17

申请号：US11933039

申请日：2007-10-31

申请人： Hyeong-Sun Hong ,  Jae-Goo Lee ,  Dong-Hyun Kim ,  Sung-Un Kwon ,  Sang-Joon Park ,  Nam-Jung Kang

发明人： Hyeong-Sun Hong ,  Jae-Goo Lee ,  Dong-Hyun Kim ,  Sung-Un Kwon ,  Sang-Joon Park ,  Nam-Jung Kang

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L21/76802 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  Y10S257/905

摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.

摘要翻译： 提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。 半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。 绝缘线限定埋入触点的宽度。 为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。 相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。 埋入的接触孔填充有导电材料以形成掩埋接触。

公开(公告)号：US07799643B2

公开(公告)日：2010-09-21

申请号：US12112438

申请日：2008-04-30

申请人： Nam-Jung Kang ,  Dong-Soo Woo ,  Hyeong-Sun Hong ,  Dong-Hyun Kim

发明人： Nam-Jung Kang ,  Dong-Soo Woo ,  Hyeong-Sun Hong ,  Dong-Hyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10855

摘要： Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.

摘要翻译： 提供制造具有自对准接触插头的半导体器件的方法。 方法包括在半导体衬底上形成下绝缘层，在下绝缘层上形成彼此平行的多个互连图案; 形成上部绝缘层，其被构造成填充在所述互连图案之间，并且形成与所述多个互连图案交叉的多个第一掩模图案，所述多个第一掩模图案中的所述第一掩模图案在所述半导体衬底上彼此平行， 层。 方法可以包括形成第二掩模图案，该第二掩模图案与多个第一掩模图案自对准，并且在多个第一掩模图案中的一个之间，使用第一和第二掩模图案蚀刻上绝缘层和下绝缘层 以及所述多个互连图案作为蚀刻掩模，以形成暴露所述半导体衬底的多个接触孔，以及在所述多个接触孔中的相应接触孔中形成多个接触插塞。 还提供了半导体器件。

公开(公告)号：US07713873B2

公开(公告)日：2010-05-11

申请号：US12151997

申请日：2008-05-12

申请人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

发明人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

IPC分类号： H01L21/44

CPC分类号： H01L29/4236 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876

摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.

摘要翻译： 在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。 在半导体衬底上形成第一层间电介质层。 形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。 位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。 在包括位线结构的半导体衬底上形成第二层间电介质层。 阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。 掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。 使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

公开(公告)号：US20100193880A1

公开(公告)日：2010-08-05

申请号：US12662150

申请日：2010-04-01

申请人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

发明人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L23/52 ,  H01L27/088

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

摘要翻译： 半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。 单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。 外围栅极图案可以设置在半导体衬底的外围有源区上。 细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。 周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。 可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

公开(公告)号：US08120123B2

公开(公告)日：2012-02-21

申请号：US12662150

申请日：2010-04-01

申请人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

发明人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L23/52 ,  H01L27/088

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

摘要翻译： 半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。 单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。 外围栅极图案可以设置在半导体衬底的外围有源区上。 细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。 周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。 可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。