公开(公告)号：US20100193880A1

公开(公告)日：2010-08-05

申请号：US12662150

申请日：2010-04-01

申请人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

发明人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L23/52 ,  H01L27/088

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

摘要翻译： 半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。 单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。 外围栅极图案可以设置在半导体衬底的外围有源区上。 细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。 周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。 可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

公开(公告)号：US08120123B2

公开(公告)日：2012-02-21

申请号：US12662150

申请日：2010-04-01

申请人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

发明人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L23/52 ,  H01L27/088

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

摘要翻译： 半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。 单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。 外围栅极图案可以设置在半导体衬底的外围有源区上。 细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。 周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。 可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

公开(公告)号：US08569860B2

公开(公告)日：2013-10-29

申请号：US12905614

申请日：2010-10-15

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L21/70

CPC分类号： H01L27/10894 ,  H01L21/823437 ,  H01L27/10873 ,  H01L27/10876 ,  H01L29/41758 ,  H01L29/66621 ,  H01L29/7834

摘要： In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a planar type device isolation gate electrode, and a width of the planar type device isolation gate electrode greater than a width of the device gate electrode.

摘要翻译： 在具有线型有源区的半导体器件和制造半导体器件的方法中，半导体器件包括限定半导体衬底中的线型有源区的器件隔离层。 彼此平行并与线型有源区相交的栅电极设置在半导体衬底的上方。 这里，栅电极包括器件栅极电极和凹陷器件隔离栅极电极。 或者，每个栅电极由器件栅电极和平面型器件隔离栅电极构成，平面型器件隔离栅电极的宽度大于器件栅电极的宽度。

公开(公告)号：US07829959B2

公开(公告)日：2010-11-09

申请号：US12486438

申请日：2009-06-17

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L27/088

CPC分类号： H01L27/10894 ,  H01L21/823437 ,  H01L27/10873 ,  H01L27/10876 ,  H01L29/41758 ,  H01L29/66621 ,  H01L29/7834

摘要： In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.

摘要翻译： 在具有线型有源区的半导体器件和制造半导体器件的方法中，半导体器件包括限定半导体衬底中的线型有源区的器件隔离层。 彼此平行并与线型有源区相交的栅电极设置在半导体衬底的上方。 这里，栅电极包括器件栅极电极和凹陷器件隔离栅极电极。 或者，每个栅电极由器件栅电极和平面型器件隔离栅电极构成，平面型器件隔离栅电极的宽度大于器件栅电极的宽度。

公开(公告)号：US20050142861A1

公开(公告)日：2005-06-30

申请号：US11020277

申请日：2004-12-27

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L21/283 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnection line in a semiconductor device includes forming an interlayer insulating layer on an underlying layer having a lower conductive layer, patterning the interlayer insulating layer to form an opening exposing the lower conductive layer, forming an additional material layer conformally on the underlying layer including the opening, anisotropically etching the additional material layer to form an opening spacer covering a sidewall of the opening, performing a wet etch process using the opening spacer as an etch mask, forming a conductive layer pattern in the opening, and performing a heat treatment on the opening spacer.

摘要翻译： 在半导体器件中形成互连线的方法包括在具有下导电层的下层上形成层间绝缘层，图案化层间绝缘层以形成露出下导电层的开口，在其上形成额外的材料层 底层，包括开口，各向异性地蚀刻附加材料层以形成覆盖开口侧壁的开口间隔件，使用开口间隔件作为蚀刻掩模执行湿蚀刻工艺，在开口中形成导电层图案，并执行 在开口垫片上进行热处理。

公开(公告)号：US20110031539A1

公开(公告)日：2011-02-10

申请号：US12905614

申请日：2010-10-15

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L27/10894 ,  H01L21/823437 ,  H01L27/10873 ,  H01L27/10876 ,  H01L29/41758 ,  H01L29/66621 ,  H01L29/7834

摘要： In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.

摘要翻译： 在具有线型有源区的半导体器件和制造半导体器件的方法中，半导体器件包括限定半导体衬底中的线型有源区的器件隔离层。 彼此平行并与线型有源区相交的栅电极设置在半导体衬底的上方。 这里，栅电极包括器件栅极电极和凹陷器件隔离栅极电极。 或者，每个栅电极由器件栅电极和平面型器件隔离栅电极构成，平面型器件隔离栅电极的宽度大于器件栅电极的宽度。

公开(公告)号：US07563699B2

公开(公告)日：2009-07-21

申请号：US11353494

申请日：2006-02-14

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L21/3205

CPC分类号： H01L27/10894 ,  H01L21/823437 ,  H01L27/10873 ,  H01L27/10876 ,  H01L29/41758 ,  H01L29/66621 ,  H01L29/7834

摘要： In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.

摘要翻译： 在具有线型有源区的半导体器件和制造半导体器件的方法中，半导体器件包括限定半导体衬底中的线型有源区的器件隔离层。 彼此平行并与线型有源区相交的栅电极设置在半导体衬底的上方。 这里，栅电极包括器件栅极电极和凹陷器件隔离栅极电极。 或者，每个栅电极由器件栅电极和平面型器件隔离栅电极构成，平面型器件隔离栅电极的宽度大于器件栅电极的宽度。

公开(公告)号：US6156636A

公开(公告)日：2000-12-05

申请号：US265890

申请日：1999-03-11

申请人： Kye-Hee Yeom ,  Kyu-Pil Lee

发明人： Kye-Hee Yeom ,  Kyu-Pil Lee

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/4763

CPC分类号： H01L21/76897

摘要： A method of forming self-aligned contact holes of a semiconductor device presents bridging from occurring between contacts formed in the holes. First, gate electrode structures are formed on a semiconductor substrate. Next, an interlayer insulating film is formed over the gate electrode structures. The interlayer insulating film is formed by forming a first oxide layer of a reflowable material over the semiconductor substrate and gate electrode structures, planarization etching the first oxide layer until the upper portions of the gate electrode structures are uncovered, and then forming a second oxide layer on the planarized upper surface of the first oxide layer. The second oxide layer is selected to have a wet etch rate that is lower than that of the first oxide layer. Then, the insulating film is etched to form a contact hole between gate electrode structures. Finally, a self-aligned contact electrically connected with the semiconductor substrate is formed by filling the contact hole with conductive material.

摘要翻译： 形成半导体器件的自对准接触孔的方法呈现出形成在孔中的触点之间的桥接。 首先，在半导体衬底上形成栅电极结构。 接着，在栅电极结构上形成层间绝缘膜。 层间绝缘膜通过在半导体衬底和栅电极结构上形成可回流材料的第一氧化物层而形成，平坦化蚀刻第一氧化物层，直到栅电极结构的上部未被覆盖，然后形成第二氧化物层 在第一氧化物层的平坦化的上表面上。 选择第二氧化物层具有低于第一氧化物层的湿蚀刻速率的湿蚀刻速率。 然后，蚀刻绝缘膜，以在栅电极结构之间形成接触孔。 最后，通过用导电材料填充接触孔来形成与半导体衬底电连接的自对准接触。

公开(公告)号：US08674420B2

公开(公告)日：2014-03-18

申请号：US12588111

申请日：2009-10-05

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.

摘要翻译： 一种半导体器件，包括：半导体衬底，包括限定半导体衬底的有源区的隔离;在半导体器件的上表面下方延伸的多个掩埋栅电极;以及沿半导体衬底上的第一方向延伸的多个位线; 其中所述多个位线连接到所述半导体衬底的相应的有源区，并且所述位线的至少一部分沿着与所述对应有源区的上表面相同和/或基本相同的平面延伸， 它是连接的。

公开(公告)号：US08486818B2

公开(公告)日：2013-07-16

申请号：US12588747

申请日：2009-10-27

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L21/76224

CPC分类号： H01L29/66621 ,  H01L21/76224 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, and a plurality of buried gate electrodes between a pair of the isolations, wherein each of the buried gate electrodes and the isolations includes a conductive layer and a capping layer.

摘要翻译： 一种半导体器件，包括包括限定半导体衬底的有源区的隔离物的半导体衬底和在一对隔离之间的多个掩埋栅电极，其中每个掩埋栅电极和隔离物包括导电层和覆盖层 。