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    Semiconductor memory device
    1.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20100237394A1

    公开(公告)日：2010-09-23

    申请号：US12659735

    申请日：2010-03-19

    申请人： Jai-Kyun Park ,  Hyeong-Sun Hong ,  Jong-Seop Lee ,  Yong-Il Kim ,  Yun-Sung Lee ,  Nam-Jung Kang ,  Jae-Hoon Song ,  Gil-Sub Kim

    发明人： Jai-Kyun Park ,  Hyeong-Sun Hong ,  Jong-Seop Lee ,  Yong-Il Kim ,  Yun-Sung Lee ,  Nam-Jung Kang ,  Jae-Hoon Song ,  Gil-Sub Kim

    IPC分类号： H01L27/108

    CPC分类号： H01L27/0207 ,  H01L27/10855

    摘要： A semiconductor memory device includes unit active regions, word lines extending in a first direction over the unit active region, bit lines extending on the word lines in a second direction substantially perpendicularly to the first direction, first pad contacts in contact with central portions of the unit active regions, the first pad contacts being arranged between the word lines, direct contacts electrically connected between the first pad contacts and the bit lines, second pad contacts in contact with edge portions of the unit active regions, the second pad contacts being arranged between the word lines and between the bit lines, buried contacts electrically connected to the second pad contacts, and capacitors electrically connected to the buried contacts.

    摘要翻译： 半导体存储器件包括单元有源区域，在单元有源区域上沿第一方向延伸的字线，沿着基本垂直于第一方向的第二方向在字线上延伸的位线，与第一方向的中心部分接触的第一焊盘触点 所述第一焊盘触点布置在所述字线之间，直接触点电连接在所述第一焊盘触点和所述位线之间，所述第二焊盘触点与所述单元有源区域的边缘部分接触，所述第二焊盘触点布置在 字线和位线之间，电连接到第二焊盘触点的埋入触点，以及电连接到埋入触点的电容器。

    Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same
    4.
    发明申请
    Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same 有权
    包括第一和第二子沟槽的半导体器件的隔离层及其形成方法

    公开(公告)号：US20060292820A1

    公开(公告)日：2006-12-28

    申请号：US11453423

    申请日：2006-06-15

    申请人： Yun-Sung Lee

    发明人： Yun-Sung Lee

    IPC分类号： H01L21/76 ,  H01L29/00

    CPC分类号： H01L21/76229 ,  H01L21/76235 ,  H01L29/1083 ,  H01L29/517

    摘要： In a device isolation layer for a p-MOS transistor and a method of forming the same, a trench oxide layer having a first and a second sub-oxide layers is formed in a trench including a first and a second sub-trenches. The first and second sub-oxide layers are formed on side and bottom surfaces of the first and second sub-trenches, respectively. The second sub-trench has a width greater than the first sub-trench. The first sub-oxide layer has a first thickness that is uniform along the side and bottom surfaces of the first sub-trench and the second sub-oxide layer has a second thickness greater than the first thickness along the side surface of the second sub-trench. A liner layer is formed on the trench oxide layer, and an insulation pattern is formed on the liner layer.

    摘要翻译： 在用于p-MOS晶体管的器件隔离层及其形成方法中，具有第一和第二次氧化物层的沟槽氧化物层形成在包括第一和第二子沟槽的沟槽中。 第一和第二子氧化物层分别形成在第一和第二子沟槽的侧面和底面上。 第二子沟槽的宽度大于第一子沟槽。 第一子氧化物层具有沿着第一子沟槽的侧表面和底表面均匀的第一厚度，并且第二子氧化物层具有大于沿着第二子沟槽的侧表面的第一厚度的第二厚度， 沟。 衬垫层形成在沟槽氧化物层上，并且在衬层上形成绝缘图案。

    Semiconductor device having landing pad and fabrication method thereof
    5.
    发明授权
    Semiconductor device having landing pad and fabrication method thereof 失效
    具有着陆垫的半导体器件及其制造方法

    公开(公告)号：US07385242B2

    公开(公告)日：2008-06-10

    申请号：US11155144

    申请日：2005-06-16

    申请人： Yun-Sung Lee ,  Joo-Sung Park

    发明人： Yun-Sung Lee ,  Joo-Sung Park

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L21/823425 ,  H01L24/05 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/05552

    摘要： A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

    摘要翻译： 可以提供包括具有上表面的半导体衬底的半导体器件。 在半导体衬底的上表面上形成多个相邻的线图形。 每个线图案包括在其上堆叠有盖层图案的线。 材料层覆盖具有线图案的半导体衬底的上表面。 衬垫接触孔位于材料层的区域内的线图案之间。 垫接触孔包括在线图案之间的下开口和位于下开口上方的上开口。 阻挡层形成在限定上部开口的侧壁上。 着陆垫基本上填充由阻挡层限定的下开口和上开口。

    Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same
    6.
    发明授权
    Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same 有权
    包括第一和第二子沟槽的半导体器件的隔离层及其形成方法

    公开(公告)号：US07652345B2

    公开(公告)日：2010-01-26

    申请号：US11453423

    申请日：2006-06-15

    申请人： Yun-Sung Lee

    发明人： Yun-Sung Lee

    IPC分类号： H01L21/20

    CPC分类号： H01L21/76229 ,  H01L21/76235 ,  H01L29/1083 ,  H01L29/517

    摘要： In a device isolation layer for a p-MOS transistor and a method of forming the same, a trench oxide layer having a first and a second sub-oxide layers is formed in a trench including a first and a second sub-trenches. The first and second sub-oxide layers are formed on side and bottom surfaces of the first and second sub-trenches, respectively. The second sub-trench has a width greater than the first sub-trench. The first sub-oxide layer has a first thickness that is uniform along the side and bottom surfaces of the first sub-trench and the second sub-oxide layer has a second thickness greater than the first thickness along the side surface of the second sub-trench. A liner layer is formed on the trench oxide layer, and an insulation pattern is formed on the liner layer.

    摘要翻译： 在用于p-MOS晶体管的器件隔离层及其形成方法中，具有第一和第二次氧化物层的沟槽氧化物层形成在包括第一和第二子沟槽的沟槽中。 第一和第二子氧化物层分别形成在第一和第二子沟槽的侧面和底面上。 第二子沟槽的宽度大于第一子沟槽。 第一子氧化物层具有沿着第一子沟槽的侧表面和底表面均匀的第一厚度，并且第二子氧化物层具有大于沿着第二子沟槽的侧表面的第一厚度的第二厚度， 沟。 衬垫层形成在沟槽氧化物层上，并且在衬层上形成绝缘图案。

    Semiconductor device having landing pad and fabrication method thereof
    8.
    发明申请
    Semiconductor device having landing pad and fabrication method thereof 失效
    具有着陆垫的半导体器件及其制造方法

    公开(公告)号：US20050230733A1

    公开(公告)日：2005-10-20

    申请号：US11155144

    申请日：2005-06-16

    申请人： Yun-Sung Lee ,  Joo-Sung Park

    发明人： Yun-Sung Lee ,  Joo-Sung Park

    IPC分类号： H01L23/522 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L21/823425 ,  H01L24/05 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10891 ,  H01L2224/05552

    摘要： A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

    摘要翻译： 可以提供包括具有上表面的半导体衬底的半导体器件。 在半导体衬底的上表面上形成多个相邻的线图形。 每个线图案包括在其上堆叠有盖层图案的线。 材料层覆盖具有线图案的半导体衬底的上表面。 衬垫接触孔位于材料层的区域内的线图案之间。 垫接触孔包括在线图案之间的下开口和位于下开口上方的上开口。 阻挡层形成在限定上部开口的侧壁上。 着陆垫基本上填充由阻挡层限定的下开口和上开口。