公开(公告)号：US20100193880A1

公开(公告)日：2010-08-05

申请号：US12662150

申请日：2010-04-01

申请人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

发明人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L23/52 ,  H01L27/088

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

摘要翻译： 半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。 单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。 外围栅极图案可以设置在半导体衬底的外围有源区上。 细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。 周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。 可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

公开(公告)号：US08120123B2

公开(公告)日：2012-02-21

申请号：US12662150

申请日：2010-04-01

申请人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

发明人： Makoto Yoshida ,  Hyeong-Sun Hong ,  Kye-Hee Yeom ,  Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L23/52 ,  H01L27/088

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.

摘要翻译： 半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。 单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。 外围栅极图案可以设置在半导体衬底的外围有源区上。 细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。 周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。 可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

公开(公告)号：US08742493B2

公开(公告)日：2014-06-03

申请号：US13285263

申请日：2011-10-31

申请人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

发明人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

IPC分类号： H01L27/108

CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/7831

摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.

摘要翻译： 半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及 多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。 导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

公开(公告)号：US20120119286A1

公开(公告)日：2012-05-17

申请号：US13285263

申请日：2011-10-31

申请人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

发明人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/7831

摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.

摘要翻译： 半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及 多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。 导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

公开(公告)号：US08450786B2

公开(公告)日：2013-05-28

申请号：US13241716

申请日：2011-09-23

申请人： Dae-Ik Kim ,  Yong-Il Kim

发明人： Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L27/108

CPC分类号： H01L27/088 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

摘要翻译： 提供了能够减小厚度的半导体器件，采用该半导体器件的电子产品及其制造方法。 制造半导体器件的方法包括制备具有第一和第二有源区的半导体衬底。 第一有源区中的第一晶体管包括第一栅极图案和第一杂质区域。 第二晶体管，第二有源区包括第二栅极图案和第二杂质区域。 第一导电图案在第一晶体管上，其中第一导电图案的至少一部分设置在与半导体衬底的上表面相同的距离处，作为第二栅极图案的至少一部分。 第一导电图案可以形成在第一晶体管上，而形成第二晶体管。

公开(公告)号：US20090072307A1

公开(公告)日：2009-03-19

申请号：US12230614

申请日：2008-09-02

申请人： Dae-Ik Kim ,  Yong-Il Kim

发明人： Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823456 ,  H01L29/1037 ,  H01L29/66583 ,  H01L29/66621

摘要： A semiconductor integrated circuit includes a semiconductor substrate, a plurality of trenches formed to extend in one direction in the semiconductor substrate, at least one connecting trench connecting at least two of the plurality of trenches to each other, a plurality of trench transistors including a plurality of gate electrodes, each gate electrode partially filling a corresponding trench, and a capping layer filling the at least one connecting trench.

摘要翻译： 半导体集成电路包括半导体衬底，形成为在半导体衬底中沿一个方向延伸的多个沟槽，至少一个将多个沟槽中的至少两个彼此连接的连接沟槽，多个沟槽晶体管，其包括多个 的栅电极，每个栅电极部分地填充相应的沟槽，以及填充所述至少一个连接沟槽的封盖层。

公开(公告)号：US08063425B2

公开(公告)日：2011-11-22

申请号：US12232498

申请日：2008-09-18

申请人： Dae-Ik Kim ,  Yong-Il Kim

发明人： Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L29/94

CPC分类号： H01L27/088 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

摘要翻译： 提供了能够减小厚度的半导体器件，采用该半导体器件的电子产品及其制造方法。 制造半导体器件的方法包括制备具有第一和第二有源区的半导体衬底。 第一有源区中的第一晶体管包括第一栅极图案和第一杂质区域。 第二晶体管，第二有源区包括第二栅极图案和第二杂质区域。 第一导电图案在第一晶体管上，其中第一导电图案的至少一部分设置在与半导体衬底的上表面相同的距离处，作为第二栅极图案的至少一部分。 第一导电图案可以形成在第一晶体管上，而形成第二晶体管。

公开(公告)号：US20090114991A1

公开(公告)日：2009-05-07

申请号：US12199458

申请日：2008-08-27

申请人： Dae-Ik Kim ,  Won-Woo Lee ,  Yong-Il Kim

发明人： Dae-Ik Kim ,  Won-Woo Lee ,  Yong-Il Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823456 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7833

摘要： A semiconductor device includes an isolation region formed in a semiconductor substrate to define an active region. First and second impurity regions spaced apart from each other are formed in the active region. A gate trench region crosses the active region between the first and second impurity regions and extends to the isolation region. A first contact structure having a sidewall in vertical alignment with a sidewall of the gate trench region adjacent to the first impurity region is provided on the first impurity region. A second contact structure having a sidewall in vertical alignment with a sidewall of the gate trench region adjacent to the second impurity region is provided on the second impurity region. A gate electrode is provided in the gate trench region. A gate dielectric layer is interposed between the gate trench region and the gate electrode.

摘要翻译： 半导体器件包括形成在半导体衬底中以限定有源区的隔离区。 在有源区域中形成彼此间隔开的第一和第二杂质区域。 栅沟槽区跨越第一和第二杂质区之间的有源区，并延伸到隔离区。 具有与第一杂质区域相邻的栅极沟槽区域的侧壁垂直对准的侧壁的第一接触结构设置在第一杂质区域上。 具有与第二杂质区域相邻的栅极沟槽区域的侧壁垂直对准的侧壁的第二接触结构设置在第二杂质区域上。 栅电极设置在栅极沟槽区域中。 栅极介电层介于栅极沟槽区域和栅电极之间。

公开(公告)号：US08343845B2

公开(公告)日：2013-01-01

申请号：US12659769

申请日：2010-03-19

申请人： Yong-Il Kim ,  Dae-Ik Kim ,  Yun-Sung Lee ,  Nam-Jung Kang

发明人： Yong-Il Kim ,  Dae-Ik Kim ,  Yun-Sung Lee ,  Nam-Jung Kang

IPC分类号： H01L21/30

CPC分类号： H01L27/0207 ,  H01G4/01 ,  H01G4/228 ,  H01G4/33 ,  H01L27/10852 ,  H01L28/91 ,  Y10T29/417

摘要： A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer.

摘要翻译： 电容器结构包括在基板上的多个下电极，下电极具有平面顶表面并且沿第一方向布置以限定下电极柱，多个下电极柱沿垂直于第一 限定下电极矩阵的方向，在至少两个相邻的下电极的上侧壁上的多个支撑件，下电极和支撑件上的电介质层，以及介电层上的上电极。

公开(公告)号：US20120007160A1

公开(公告)日：2012-01-12

申请号：US13241716

申请日：2011-09-23

申请人： Dae-Ik Kim ,  Yong-Il Kim

发明人： Dae-Ik Kim ,  Yong-Il Kim

IPC分类号： H01L27/108

CPC分类号： H01L27/088 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

摘要翻译： 提供了能够减小厚度的半导体器件，采用该半导体器件的电子产品及其制造方法。 制造半导体器件的方法包括制备具有第一和第二有源区的半导体衬底。 第一有源区中的第一晶体管包括第一栅极图案和第一杂质区域。 第二晶体管，第二有源区包括第二栅极图案和第二杂质区域。 第一导电图案在第一晶体管上，其中第一导电图案的至少一部分设置在与半导体衬底的上表面相同的距离处，作为第二栅极图案的至少一部分。 第一导电图案可以形成在第一晶体管上，而形成第二晶体管。