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1.发明授权公开(公告)号：US06744087B2
公开(公告)日：2004-06-01
申请号：US10256881
申请日：2002-09-27
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L27/11507 , H01L27/11585 , H01L27/1159 , H01L29/6684 , H01L29/78391
摘要： A vertical ferroelectric gate field-effect transistor (FeGFET) device comprises a substrate and a first drain/source electrode formed on an upper surface of the substrate. An electrically conductive channel region is formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode. The FeGFET device further comprises a ferroelectric gate region formed on at least one side wall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region. The ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes. A non-volatile memory array can be formed comprising a plurality of FeGFET devices.
摘要翻译： 垂直铁电栅极场效应晶体管（FeGFET）器件包括形成在衬底的上表面上的衬底和第一漏极/源极。 在第一漏/源电极的上表面上形成导电沟道区，并与第一漏/源电极电接触。 FeGFET器件还包括形成在通道区域的至少一个侧壁上的铁电栅极区域，与铁电栅极区域电接触的至少一个栅极电极和形成在沟道区域的上表面上的第二漏极/源极电极，以及 电接触通道区域。 铁电栅极区域响应于施加在栅极电极和第一和第二漏极/源极电极中的至少一个之间的电位而选择性地极化。 可以形成包括多个FeGFET装置的非易失性存储器阵列。
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2.发明申请公开(公告)号：US20080263383A1
公开(公告)日：2008-10-23
申请号：US12163493
申请日：2008-06-27
IPC分类号： G06F1/04
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
摘要翻译： 在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。 电子元件的工作频率根据性能参数进行调整。 性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。 也可以通过错误检测电路来确定性能统计。 如果检测到错误，则可以减少工作频率。
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3.发明授权公开(公告)号：US06894916B2
公开(公告)日：2005-05-17
申请号：US10256715
申请日：2002-09-27
申请人： William Robert Reohr , Li-Kong Wang
发明人： William Robert Reohr , Li-Kong Wang
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , G11C5/06
CPC分类号： G11C11/22
摘要： An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.
摘要翻译： 改进的非易失性存储器阵列包括多个存储器单元，至少一个存储器单元包括用于存储至少一个存储器单元的逻辑状态的三端非易失性存储元件。 存储器阵列还包括可操作地耦合到存储器单元的多个写入线，用于选择性地将存储器阵列中的一个或多个存储器单元的逻辑状态写入，并且可操作地耦合到存储器单元的多个位线和字线用于选择性地 读取和写入存储器阵列中的一个或多个存储器单元的逻辑状态。 有利地，存储器阵列被配置为消除对可操作地耦合到至少一个存储器单元中的对应的非易失性存储元件的通过栅极的需要。
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公开(公告)号：US06389505B1
公开(公告)日：2002-05-14
申请号：US09196086
申请日：1998-11-19
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G06F12/0802
摘要： A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.
摘要翻译： 一种用于通过仅恢复在分配的数据保留时间内未被读取或写入的那些单元来减少维持DRAM中的数据所需的刷新动作数量的系统和方法。 一个实施例描述了应用于DRAM高速缓存的还原跟踪系统。 还原跟踪系统可以替代地应用于具有信息重复的任何存储器架构。 例如，可以通过记录和更新DRAM中的一个或多个数据条目的刷新状态来减少维护DRAM中的数据条目所需的刷新动作的数量; 并使那些具有过期状态的数据条目无效。 因此，可以使更多的存储器带宽可用于计算机系统。
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公开(公告)号：US08495444B2
公开(公告)日：2013-07-23
申请号：US12163493
申请日：2008-06-27
IPC分类号： G01R31/30
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
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6.发明授权公开(公告)号：US07475320B2
公开(公告)日：2009-01-06
申请号：US10643549
申请日：2003-08-19
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
摘要翻译： 在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。 电子元件的工作频率根据性能参数进行调整。 性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。 也可以通过错误检测电路来确定性能统计。 如果检测到错误，则可以减少工作频率。
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公开(公告)号：US07447273B2
公开(公告)日：2008-11-04
申请号：US10708240
申请日：2004-02-18
申请人： Louis L. Hsu , Carl Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl Radens , Li-Kong Wang
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译： 提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。 提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。 连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射器连接到该输出信号线来代替故障数据发射器。 在一个优选形式中，连接元件包括保险丝和反熔丝。 在另一种形式中，连接元件包括微机电（MEM）开关。 连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。
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公开(公告)号：US07041525B2
公开(公告)日：2006-05-09
申请号：US10751205
申请日：2004-01-02
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
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公开(公告)号：US20050282323A1
公开(公告)日：2005-12-22
申请号：US11202834
申请日：2005-08-12
申请人： Louis Hsu , Li-Kong Wang
发明人： Louis Hsu , Li-Kong Wang
IPC分类号： H01L21/20 , H01L27/12 , D06N7/04 , G11B5/64 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/12 , H01L21/02381 , H01L21/0243 , H01L21/02527 , Y10T428/12674 , Y10T428/24355 , Y10T428/24802 , Y10T428/24942 , Y10T428/30
摘要： A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.
摘要翻译： 提出了混合基板，即由不同材料制造的基板及其制造方法。 混合基板被配置为在其上制造两个以上的不同器件，具有高导热性，并且被配置用于在其上构图互连以互连在混合基板上制造的不同器件。
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10.发明授权Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating 失效含有难熔金属 - 硅 - 氮电阻元件的紧凑SRAM单元及其制造方法公开(公告)号：US06777286B2
公开(公告)日：2004-08-17
申请号：US10616243
申请日：2003-07-08
申请人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
发明人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.
摘要翻译： 描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供 衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。 本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。
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