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    Non-volatile memory using ferroelectric gate field-effect transistors
    1.
    发明授权
    Non-volatile memory using ferroelectric gate field-effect transistors 有权
    使用铁电栅极场效应晶体管的非易失性存储器

    公开(公告)号：US06744087B2

    公开(公告)日：2004-06-01

    申请号：US10256881

    申请日：2002-09-27

    申请人： James A. Misewich ,  William Robert Reohr ,  Alejandro Gabriel Schrott ,  Li-Kong Wang

    发明人： James A. Misewich ,  William Robert Reohr ,  Alejandro Gabriel Schrott ,  Li-Kong Wang

    IPC分类号： H01L2976

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

    摘要： A vertical ferroelectric gate field-effect transistor (FeGFET) device comprises a substrate and a first drain/source electrode formed on an upper surface of the substrate. An electrically conductive channel region is formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode. The FeGFET device further comprises a ferroelectric gate region formed on at least one side wall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region. The ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes. A non-volatile memory array can be formed comprising a plurality of FeGFET devices.

    摘要翻译： 垂直铁电栅极场效应晶体管（FeGFET）器件包括形成在衬底的上表面上的衬底和第一漏极/源极。 在第一漏/源电极的上表面上形成导电沟道区，并与第一漏/源电极电接触。 FeGFET器件还包括形成在通道区域的至少一个侧壁上的铁电栅极区域，与铁电栅极区域电接触的至少一个栅极电极和形成在沟道区域的上表面上的第二漏极/源极电极，以及 电接触通道区域。 铁电栅极区域响应于施加在栅极电极和第一和第二漏极/源极电极中的至少一个之间的电位而选择性地极化。 可以形成包括多个FeGFET装置的非易失性存储器阵列。

    Tunable thin film optical devices and fabrication methods for tunable thin film optical devices
    2.
    发明授权
    Tunable thin film optical devices and fabrication methods for tunable thin film optical devices 有权
    可调谐薄膜光学器件及可调谐薄膜光学器件的制造方法

    公开(公告)号：US07002646B2

    公开(公告)日：2006-02-21

    申请号：US10388538

    申请日：2003-03-17

    申请人： James A. Misewich ,  Alejandro Gabriel Schrott

    发明人： James A. Misewich ,  Alejandro Gabriel Schrott

    IPC分类号： G02F1/1347 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/13

    CPC分类号： G02F1/0551 ,  G02F2001/213 ,  G02F2201/34 ,  G02F2203/12

    摘要： Thin film structures include electro-optic materials and transparent conducting materials which are combined to fabricate vertical optical devices. The electro-optic materials are responsive to an electric field to change an optical characteristic. For example, a modulator can be fabricated by making a dielectric mirror from such materials by alternating the electro-optic material with the transparent conducting material. The mirror reflection band can then be tuned by applying an electric field between the transparent conducting layers.

    摘要翻译： 薄膜结构包括电光材料和透明导电材料，其被组合以制造垂直光学装置。 电光材料响应于电场以改变光学特性。 例如，可以通过使电光材料与透明导电材料交替而由这种材料制成电介质反射镜来制造调制器。 然后可以通过在透明导电层之间施加电场来调整镜面反射带。

    Cross-point memory architecture with improved selectivity
    3.
    发明授权
    Cross-point memory architecture with improved selectivity 有权
    具有提高选择性的交叉点内存架构

    公开(公告)号：US07046550B1

    公开(公告)日：2006-05-16

    申请号：US11037707

    申请日：2005-01-18

    申请人： William Robert Reohr ,  Alejandro Gabriel Schrott

    发明人： William Robert Reohr ,  Alejandro Gabriel Schrott

    IPC分类号： G11C16/04

    CPC分类号： G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/78 ,  G11C2213/79

    摘要： A cross-point memory includes a plurality of memory cells, a plurality of global word lines, a plurality of local word lines, and a plurality of global bit lines. At least a given one of the global word lines is configurable for conveying a write current for selectively writing a logical state of one or more of the memory cells. Each of the local word lines is connected to at least one of the memory cells for assisting in writing a logical state of the at least one memory cell corresponding thereto. Each of the global bit lines is connected to at least one of the memory cells for writing a logical state of the memory cell corresponding thereto. The memory further includes a plurality of selection circuits, each of the selection circuits being operative to electrically connect a given one of the local word lines to a given one of the global word lines in response to a control signal applied thereto. During a write operation directed to at least one selected memory cell, the write current passes through the selected memory cell for writing the logical state of the selected memory cell.

    摘要翻译： 交叉点存储器包括多个存储器单元，多个全局字线，多个局部字线和多个全局位线。 至少一个全局字线中的一个可配置为传送用于选择性地写入一个或多个存储器单元的逻辑状态的写入电流。 每个本地字线连接到至少一个存储器单元，用于辅助写入与之对应的至少一个存储单元的逻辑状态。 每个全局位线连接到用于写入对应于其的存储单元的逻辑状态的至少一个存储单元。 存储器还包括多个选择电路，每个选择电路可操作以响应于施加到其上的控制信号将本地字线中的给定一个电气连接到给定的一个全局字线。 在针对至少一个所选择的存储单元的写入操作期间，写入电流通过所选择的存储器单元以写入所选存储单元的逻辑状态。

    Scaled-down phase change memory cell in recessed heater
    4.
    发明授权
    Scaled-down phase change memory cell in recessed heater 有权
    嵌入式加热器中的缩小相变存储单元

    公开(公告)号：US08426967B2

    公开(公告)日：2013-04-23

    申请号：US11620138

    申请日：2007-01-05

    申请人： Eric Andrew Joseph ,  Chung Hon Lam ,  Alejandro Gabriel Schrott

    发明人： Eric Andrew Joseph ,  Chung Hon Lam ,  Alejandro Gabriel Schrott

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/06

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

    摘要： A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.

    摘要翻译： 可配置为用作非易失性存储元件的半导体结构包括第一电极，形成在第一电极的上表面的至少一部分上的绝缘层和穿过绝缘层并且相对于第一电极的上表面凹陷的柱 绝缘层。 支柱包括形成在第一电极的上表面的至少一部分上的加热器和形成在靠近加热器的绝缘层的侧壁上和在加热器的上表面的至少一部分上的套环。 该结构还包括形成在绝缘层的上表面的至少一部分上并基本上填充由加热器的上表面限定的体积和套环的上表面的至少一部分的PCM层。 第二电极形成在相变材料层的上表面的至少一部分上。

    Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement
    6.
    发明授权
    Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement 有权
    具有同心相变材料的非易失性存储单元围绕柱布置形成

    公开(公告)号：US07989796B2

    公开(公告)日：2011-08-02

    申请号：US12051389

    申请日：2008-03-19

    申请人： Chung Hon Lam ,  Alejandro Gabriel Schrott

    发明人： Chung Hon Lam ,  Alejandro Gabriel Schrott

    IPC分类号： H01L47/00

    CPC分类号： H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1691

    摘要： A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

    摘要翻译： 存储单元包括第一特征和第二特征。 第二特征包括介电材料并限定至少部分地覆盖第一特征的开口。 在第一特征上形成第三特征并且部分地填充第二特征中的开口。 此外，相变材料至少填充第二特征和第三特征之间的体积。 响应于将切换信号施加到存储器单元，相变材料的至少一部分可操作以在较低和较高的电阻状态之间切换。

    Phase change memory cell design with adjusted seam location
    7.
    发明授权
    Phase change memory cell design with adjusted seam location 有权
    相变存储单元设计，具有调整的接缝位置

    公开(公告)号：US07525176B2

    公开(公告)日：2009-04-28

    申请号：US11668992

    申请日：2007-01-30

    申请人： Matthew J. Breitwisch ,  Thomas Happ ,  Alejandro Gabriel Schrott

    发明人： Matthew J. Breitwisch ,  Thomas Happ ,  Alejandro Gabriel Schrott

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L45/144 ,  G11C13/0004 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    摘要： A memory cell comprises a lower electrode, a phase change feature, a spacer feature, and a dielectric layer. The lower electrode comprises a first surface region as well as a second surface region that is raised in relation to the first surface region. The phase change feature is disposed on the second surface region of the lower electrode and has one or more sidewalls. The spacer feature is also disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature. The dielectric layer is formed at least partially on top of the first surface region of the lower electrode and abutting the spacer feature.

    摘要翻译： 存储单元包括下电极，相变特征，间隔物特征和介电层。 下电极包括第一表面区域以及相对于第一表面区域升高的第二表面区域。 相变特征设置在下电极的第二表面区域上并且具有一个或多个侧壁。 间隔件特征也设置在下电极的第二表面区域上并抵靠相变特征的一个或多个侧壁。 电介质层至少部分地形成在下电极的第一表面区域的顶部上并邻接间隔物特征。