公开(公告)号：US07025596B2

公开(公告)日：2006-04-11

申请号：US10867345

申请日：2004-06-14

申请人： James A. Zollo ,  Bonnie J. Bachman ,  Alan R. Beatty ,  Stephen O. Bozzone ,  Nitin B. Desai ,  Ronald J. Kelley ,  Rami C. Levy

发明人： James A. Zollo ,  Bonnie J. Bachman ,  Alan R. Beatty ,  Stephen O. Bozzone ,  Nitin B. Desai ,  Ronald J. Kelley ,  Rami C. Levy

IPC分类号： H01R33/00

CPC分类号： H01R4/64 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01R12/7076 ,  Y10T428/24033 ,  Y10T442/3504 ,  Y10T442/3659 ,  Y10T442/3683 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method and apparatus form electrical connections between electronic circuits and conductive threads (102, 104, 106, 108) that are interwoven into textile material (130). Electronic circuits (128), such as semiconductor dies, are connected to a carrier (132) and electrical connections (136) are made to conductive connection areas (110, 112, 114, 116) on the carrier (132). Conductive stitching (202, 204, 206, 208) provides electrical contacts for both the conductive connection areas (110, 112, 114, 116) on the carrier (132) and the conductive threads (102, 104, 106, 108) that are interwoven into the textile material (130). Optionally, a thin, flexible substrate material (132) is perforated during the stitching process.

摘要翻译： 一种方法和装置形成电子电路与交织到纺织材料（130）中的导电丝线（102,104,106,108）之间的电连接。 诸如半导体管芯的电子电路（128）连接到载体（132），并且电连接（136）被制成载体（132）上的导电连接区域（110,112,114,116）。 导电缝合（202,204,206,208）为载体（132）上的导电连接区域（110,112,114,116）和导电线（102,104,106,108）两者提供电接触，​​导电连接区域 交织到纺织材料（130）中。 可选地，在缝合过程期间穿孔薄的柔性基底材料（132）。

公开(公告)号：US06972382B2

公开(公告)日：2005-12-06

申请号：US10626242

申请日：2003-07-24

申请人： James A. Zollo ,  Nitin B. Desai

发明人： James A. Zollo ,  Nitin B. Desai

IPC分类号： H05K3/46 ,  H05K1/11 ,  H01R12/04

CPC分类号： H05K3/4623 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2201/096 ,  Y10T29/49126 ,  Y10T29/49155

摘要： A multilayer circuit board (50) includes a plurality of substrate cores (34 and 44), an adhesive/bonding layer (55) between at least two among the plurality of substrate cores, and a microvia (35 and 45) in each of at least two of the plurality of substrate cores. The microvia includes a conductive interconnection (39) between a top conductive surface and a bottom conductive surface of each of the plurality of substrate cores and the microvia in a first substrate core is arranged to be inverted relative to a microvia in a second substrate core. The multilayer circuit board can further include a plated through-hole (54) through the plurality of substrate cores and the adhesive/bonding layer such that at least two among the top conductive surfaces (32 or 46) and the bottom conductive surfaces (36 or 42) of the plurality of substrate cores are connected.

摘要翻译： 多层电路板（50）包括多个基板芯（34和44），多个基板芯中的至少两个之间的粘合/粘合层（55）和每个基板芯中的微孔（35和45） 多个基板芯中的至少两个。 微孔包括在多个基板芯的每个的顶部导电表面和底部导电表面之间的导电互连（39），并且第一基板芯中的微孔被布置成相对于第二基板芯中的微孔而相反。 多层电路板还可以包括通过多个衬底芯和粘合/粘合层的电镀通孔（54），使得顶部导电表面（32或46）和底部导电表面（36或36）中的至少两个 连接多个基板芯的42）。

公开(公告)号：US07286366B2

公开(公告)日：2007-10-23

申请号：US11089065

申请日：2005-03-24

申请人： James A. Zollo ,  John K. Arledge ,  Nitin B. Desai

发明人： James A. Zollo ,  John K. Arledge ,  Nitin B. Desai

IPC分类号： H05K1/18

CPC分类号： H05K1/184 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4611 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49139

摘要： A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.

摘要翻译： 多层衬底组件（80）包括在多个堆叠的预处理衬底内的至少一个嵌入部件（52）。 每个预处理衬底可以具有芯电介质（14），在芯电介质的相对侧上的图案化导电表面（12和16）以及至少两个相邻堆叠的预处理衬底中的每一个中的至少一个孔（18） 使得至少两个孔基本对准在彼此的顶部上，形成单个孔（19）。 组件还包括在相应的预处理衬底的顶表面和底表面之间的经处理的粘合剂层（48）。 将嵌入式部件放置在单个孔中，并在嵌入部件与单个孔的周围壁之间形成间隙（67＆66）。 当组件被偏压时，经处理的粘合剂层填充间隙以形成具有与多个预处理基板交叉的嵌入部件的组件。

公开(公告)号：US07594318B2

公开(公告)日：2009-09-29

申请号：US11854098

申请日：2007-09-12

申请人： James A. Zollo ,  John K. Arledge ,  Nitin B. Desai

发明人： James A. Zollo ,  John K. Arledge ,  Nitin B. Desai

IPC分类号： H05K1/18 ,  H05K3/30 ,  H05K1/16

CPC分类号： H05K1/184 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4611 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49139

摘要： A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.

摘要翻译： 多层衬底组件（80）包括在多个堆叠的预处理衬底内的至少一个嵌入部件（52）。 每个预处理衬底可以具有芯电介质（14），在芯电介质的相对侧上的图案化导电表面（12和16）以及至少两个相邻堆叠的预处理衬底中的每一个中的至少一个孔（18） 使得至少两个孔基本对准在彼此的顶部上，形成单个孔（19）。 组件还包括在相应的预处理衬底的顶表面和底表面之间的经处理的粘合剂层（48）。 将嵌入式部件放置在单个孔中，并在嵌入部件与单个孔的周围壁之间形成间隙（67＆66）。 当组件偏压时，经处理的粘合剂层填充间隙以形成具有与多个预处理衬底交叉的嵌入部件的组件。