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公开(公告)号：US07132357B2
公开(公告)日：2006-11-07
申请号：US11238894
申请日：2005-09-29
IPC分类号： H01L21/44
CPC分类号： H05K1/0218 , H01L2223/6622 , H05K1/0221 , H05K1/0222 , H05K1/113 , H05K3/4644 , H05K9/0039 , H05K2201/0715 , H05K2201/09036 , H05K2201/09509 , H05K2201/09809 , H05K2201/09972 , H05K2201/09981 , H05K2201/10553 , H05K2201/10969 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： A method for shielding one or more circuits (21, 21′) of a printed circuit board includes depositing a layer of dielectric material (43) over a printed circuit board substrate (22) and the printed circuits (21, 21′), creating a trench-like opening (44) in the dielectric layer (43) such that the trench-like opening (44) surrounds the one or more circuits (21, 21′) to be shielded, depositing a layer of metal (27) over the layer of dielectric material (43) and within the trench-like openings (44), creating a solder pad (24) at each location where an electrical connection is to be made to the printed circuits (21, 21′) by removing a border of the metal layer (27) surrounding each connection location, and providing a microvia (25) through each solder pad (24) penetrating the dielectric layer (43) and terminating at the metal of the printed circuit (21, 21′).
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公开(公告)号：US06515222B2
公开(公告)日：2003-02-04
申请号：US09775460
申请日：2001-02-05
IPC分类号： H05K900
CPC分类号： H05K1/0218 , H01L2223/6622 , H05K1/0221 , H05K1/0222 , H05K1/113 , H05K3/4644 , H05K9/0039 , H05K2201/0715 , H05K2201/09036 , H05K2201/09509 , H05K2201/09809 , H05K2201/09972 , H05K2201/09981 , H05K2201/10553 , H05K2201/10969 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： Methods and apparatus for forming a metal shield on a printed circuit board (10) include a layer of dielectric material (23) one or more printed circuits (21) on the layer of dielectric material (23), a layer of metal (27) on the layer of dielectric material (23), a metal-clad trench or opening surrounding the printed circuit (44) and electrically connected to the layer of metal(27), a solder pad (24) on the layer of dielectric material (23), a microvia (25) through the solder pad (24) and the layer of dielectric material (23), and electrical components (11) soldered to the solder pads (24) and to the printed circuit (21).
摘要翻译： 在印刷电路板（10）上形成金属屏蔽的方法和装置包括介电材料层（23），介电材料层（23）上的一个或多个印刷电路（21），金属层（27） 在电介质材料层（23）上，围绕印刷电路（44）并电连接到金属层（27）的金属包覆沟槽或开口，介电材料层（23）上的焊盘（24） ），通过焊盘（24）和电介质材料层（23）的微孔（25）以及焊接到焊盘（24）和印刷电路（21）的电气部件（11）。
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公开(公告)号：US5382471A
公开(公告)日：1995-01-17
申请号：US12824
申请日：1993-02-03
CPC分类号： C04B41/009 , C04B41/52 , C04B41/89 , C23C14/022 , C23C14/18 , C23C26/00 , H05K3/388 , Y10T428/265
摘要： A metallized aluminum nitride substrate (40) has a first layer (42) of deposited metal, comprising chromium, chromium oxide, and an aluminum nitride/chromium oxide complex represented by the formulaAl.sub.a N.sub.b O.sub.c Cr.sub.dwhere a, b, c and d are numbers representing relative combining ratios. The first layer is formed by sputtering about 10-500 .ANG.ngstroms of chromium onto the substrate under vacuum, and then heating the substrate in an oxygen-containing atmosphere at conditions of time and temperature sufficient to convert at least portions of the deposited chromium to chromium oxide, in order to form an adherent metal system. A second layer (44) of metal such as chromium covers the first layer. A third layer (46) of metal is deposited on the second layer in a manner sufficient to prevent oxidation of the second layer.
摘要翻译： 金属化氮化铝衬底（40）具有沉积金属的第一层（42），其包含铬，氧化铬和由式AlaNbOcCrd表示的氮化铝/铬氧化物络合物，其中a，b，c和d表示相对 组合比。 第一层是通过在真空下将大约10-500埃的铬溅射到衬底上形成的，然后在足够的时间和温度的条件下在含氧气氛中加热衬底，以将至少部分沉积的铬转化成铬 氧化物，以形成粘附金属体系。 金属如铬的第二层（44）覆盖第一层。 金属的第三层（46）以足以防止第二层氧化的方式沉积在第二层上。
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4.发明授权公开(公告)号：US07286366B2
公开(公告)日：2007-10-23
申请号：US11089065
申请日：2005-03-24
申请人： James A. Zollo , John K. Arledge , Nitin B. Desai
发明人： James A. Zollo , John K. Arledge , Nitin B. Desai
IPC分类号： H05K1/18
CPC分类号： H05K1/184 , H05K1/185 , H05K3/4046 , H05K3/4611 , H05K2201/10636 , Y02P70/611 , Y10T29/41 , Y10T29/417 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49137 , Y10T29/49139
摘要： A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.
摘要翻译： 多层衬底组件（80）包括在多个堆叠的预处理衬底内的至少一个嵌入部件（52）。 每个预处理衬底可以具有芯电介质（14），在芯电介质的相对侧上的图案化导电表面（12和16）以及至少两个相邻堆叠的预处理衬底中的每一个中的至少一个孔（18） 使得至少两个孔基本对准在彼此的顶部上，形成单个孔（19）。 组件还包括在相应的预处理衬底的顶表面和底表面之间的经处理的粘合剂层（48）。 将嵌入式部件放置在单个孔中，并在嵌入部件与单个孔的周围壁之间形成间隙（67＆66）。 当组件被偏压时，经处理的粘合剂层填充间隙以形成具有与多个预处理基板交叉的嵌入部件的组件。
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公开(公告)号：US06990734B2
公开(公告)日：2006-01-31
申请号：US10263006
申请日：2002-10-02
IPC分类号： H05K3/34
CPC分类号： H05K1/0218 , H01L2223/6622 , H05K1/0221 , H05K1/0222 , H05K1/113 , H05K3/4644 , H05K9/0039 , H05K2201/0715 , H05K2201/09036 , H05K2201/09509 , H05K2201/09809 , H05K2201/09972 , H05K2201/09981 , H05K2201/10553 , H05K2201/10969 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： Methods for forming a metal shield on a printed circuit board (10) include depositing a first layer of metal (41) on a substrate (22) of the printed circuit board (10), depositing a first layer of dielectric material (42) on the first layer of metal (41), printing one or more circuits (21, 21′) on the first dielectric layer (42), depositing a second layer of dielectric material (43) over the one or more printed circuits (21, 21′), forming a trench-like opening (44) in the two layers of dielectric material (42, 43) surrounding the one or more printed circuits (21, 21′) so that the metal of the first layer (41) is exposed by the trench-like opening (44), depositing a second layer of metal (27) on the second layer of dielectric material (43) such that the second layer of metal (27) plates the trench-like opening (44) and makes electrical contact with the first metal layer (41).
摘要翻译： 在印刷电路板（10）上形成金属屏蔽的方法包括在印刷电路板（10）的基板（22）上沉积第一金属层（41），将第一层介电材料（42）沉积在 所述第一金属层（41），在所述第一介电层（42）上印刷一个或多个电路（21,21'），在所述一个或多个印刷电路（21,21）上沉积第二介电材料层 '），在围绕所述一个或多个印刷电路（21,21'）的两层介电材料（42,43）中形成沟槽状开口（44），使得第一层（41）的金属暴露 通过所述沟槽状开口（44），在所述第二介电材料层（43）上沉积第二金属层（27），使得所述第二金属层（27）平坦化所述沟槽状开口（44）并使 与第一金属层（41）电接触。
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6.发明授权
公开(公告)号：US5591480A
公开(公告)日：1997-01-07
申请号：US517392
申请日：1995-08-21
IPC分类号： G02F1/1345 , H01L21/48 , H03H3/08 , H05K3/06 , H05K3/24 , B05D5/12 , C23C14/00 , C25D5/02 , H01L21/465
CPC分类号： H05K3/243 , H01L21/4846 , H03H3/08 , G02F1/1345 , H05K2201/0326 , H05K2203/0384 , H05K2203/095 , H05K3/062 , H05K3/064
摘要： One method for fabricating solderable pads (406) onto a substrate (220) for direct chip attachment uses a multilayer metallization coating (500). The coating has a bottom layer (202) of indium-tin oxide, with an intermediate layer (204) of copper and a top layer (206) of indium-tin oxide. A masking layer (208) is deposited on the active display area (402) of the substrate, leaving the bonding pads uncovered. The revealed bonding pads are then plasma etched, using the polyimide as an etch resist, and the top layer of ITO is selectively removed to reveal the underlying copper layer. The exposed copper layer (204) is then plated with a solderable metal to the desired thickness to form bonding pads that may be used with direct chip attachment schemes.
摘要翻译： 用于将可焊焊盘（406）制造到用于直接芯片附接的基板（220）上的一种方法使用多层金属化涂层（500）。 涂层具有铟锡氧化物的底层（202），其中铜的中间层（204）和氧化铟锡的顶层（206）。 掩模层（208）沉积在衬底的有源显示区域（402）上，留下焊盘未被覆盖。 然后使用聚酰亚胺作为抗蚀剂，然后等离子体蚀刻所揭示的接合焊盘，并且选择性地去除ITO的顶层以露出下面的铜层。 然后将暴露的铜层（204）用可焊接金属镀覆至所需厚度，以形成可与直接芯片附接方案一起使用的焊盘。
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公开(公告)号：US5395740A
公开(公告)日：1995-03-07
申请号：US10224
申请日：1993-01-27
CPC分类号： H05K3/048 , G02F1/13439 , G03F7/00 , G03F7/0035 , G03F7/2022 , H01L51/0021
摘要： A method of forming electrode patterns on a substrate. A transparent substrate (10) is patterned with a photoresist layer (14) on the front side so that portions (18) of the substrate are revealed. A metal oxide layer (12) is deposited on the patterned photoresist layer and the revealed portions of the substrate. The patterned photoresist layer is then exposed to actinic radiation (19) through the back side (25) of the transparent substrate. The photoresist pattern (20) is removed, carrying with it those portions of the metal oxide layer deposited on the photoresist layer, forming an electrode pattern (22) by a lift-off technique.
摘要翻译： 在基板上形成电极图案的方法。 透明基板（10）被图案化，在前侧具有光致抗蚀剂层（14），从而露出基板的部分（18）。 金属氧化物层（12）沉积在图案化的光刻胶层和衬底的露出部分上。 然后将图案化的光致抗蚀剂层通过透明基底的背面（25）暴露于光化辐射（19）。 去除光致抗蚀剂图案（20），携带沉积在光致抗蚀剂层上的金属氧化物层的那些部分，通过剥离技术形成电极图案（22）。
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公开(公告)号：US5869899A
公开(公告)日：1999-02-09
申请号：US78115
申请日：1998-05-13
申请人： John K. Arledge , Thomas J. Swirbel
发明人： John K. Arledge , Thomas J. Swirbel
CPC分类号： H05K3/4046 , H01L21/4846 , H01L21/4853 , H01L2924/0002 , H05K2201/0347 , H05K2201/10234 , H05K3/4644
摘要： A method of creating high density interlayer interconnects on circuit carrying substrates. A circuit pattern (20) is formed on one side of a substrate (10), and gold balls (30) are selectively placed on the circuit pattern using a thermosonic ball bonder. A liquid solution of a polymer is cast directly on the substrate and the etched circuit pattern such that only the upper portion of each gold ball is revealed when the liquid polymer solution is then dried and cured to form a dry film (40). A second layer of metal is then deposited directly on the dry film, such that it is electrically and mechanically connected to the exposed top of the gold balls. A second circuit pattern (50) is then formed in the second layer of metal. The resulting high density interconnect has two circuit layers separated by a dielectric layer. Each circuit layer is connected to the other by the gold balls that serve as conductive vias.
摘要翻译： 一种在电路承载衬底上产生高密度层间互连的方法。 电路图案（20）形成在基板（10）的一侧上，并且使用热球球接合器将金球（30）选择性地放置在电路图案上。 将聚合物的液体溶液直接浇铸在基材和蚀刻电路图案上，使得仅当液体聚合物溶液干燥和固化以形成干膜（40）时，才会露出每个金球的上部。 然后将第二层金属直接沉积在干膜上，使得其与金球的暴露的顶部电气和机械连接。 然后在第二金属层中形成第二电路图案（50）。 所得到的高密度互连具有由介电层隔开的两个电路层。 每个电路层通过用作导电通孔的金球彼此连接。
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公开(公告)号：US5576052A
公开(公告)日：1996-11-19
申请号：US635822
申请日：1996-04-22
CPC分类号： H05K3/4076 , C23C18/165 , C23C18/405 , C23C28/023 , H05K3/422 , C23C18/1603 , C23C18/1653 , C23C18/1689 , H05K3/427
摘要： A method of manufacturing high aspect ratio plated through holes in a circuit carrying substrate. High aspect ratio apertures or holes (16) are formed in a substrate (10). A thin film of copper (20) is sputtered onto the substrate and in the apertures that a macroscopically discontinuous copper film (26) is formed on part of the aperture walls. The macroscopically discontinuous copper film is substantially thinner than the copper film that is deposited on the surface. A catalytic copper coating (30) is plated directly on the vacuum deposited thin film of copper by electroless copper plating in a manner sufficient to form a macroscopically continuous copper layer on the aperture walls.
摘要翻译： 一种在电路承载衬底中制造高纵横比电镀通孔的方法。 在衬底（10）中形成高纵横比孔或孔（16）。 将铜（20）的薄膜溅射到基板上和孔中，在孔壁的一部分上形成宏观不连续的铜膜（26）。 宏观不连续的铜膜比沉积在表面上的铜膜薄得多。 催化铜涂层（30）通过化学镀铜直接镀在真空沉积的铜薄膜上，以足以在孔壁上形成宏观连续的铜层。
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10.发明授权Method for fabricating LCD substrates having solderable die attach pads 失效一种用于制造具有可焊接管芯附接焊盘的LCD基板的方法
公开(公告)号：US5529863A
公开(公告)日：1996-06-25
申请号：US503141
申请日：1995-07-17
申请人： Thomas J. Swirbel , John K. Arledge
发明人： Thomas J. Swirbel , John K. Arledge
IPC分类号： G02F1/13 , G02F1/1345 , C09K19/00
CPC分类号： G02F1/13452 , G02F1/1345
摘要： A method for fabricating solderable pads (106) onto a glass substrate (101) includes the step of depositing a seed metallization layer (step 406) after the polyimide layer is cured (step 404) but prior to buffing the alignment layer (step 414). The seed metallization layer can done by, for example, sputter depositing indium-tin, tin or copper.
摘要翻译： 用于在玻璃基板（101）上制造可焊接焊盘（106）的方法包括在聚酰亚胺层固化（步骤404）之后但在抛光对准层之前沉积种子金属化层（步骤406）的步骤（步骤414） 。 种子金属化层可以通过例如溅射沉积铟锡，锡或铜来完成。
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