公开(公告)号：US06430678B1

公开(公告)日：2002-08-06

申请号：US09363463

申请日：1999-07-29

申请人： James Allan Kahle ,  Hung Qui Le ,  Lee Evan Eisen ,  John Edward Derrick ,  Robert William Hay

发明人： James Allan Kahle ,  Hung Qui Le ,  Lee Evan Eisen ,  John Edward Derrick ,  Robert William Hay

IPC分类号： G06F930

CPC分类号： G06F9/30018 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

摘要： An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.

摘要翻译： 通过使用指令排序器单元记分板提供XER记分板功能。 如果XER由前一条指令使用，记分板位将被置位。 如果获取使用XER的新指令，则生成对XER的虚拟读取以测试记分板位以确定记分板位是否设置。 如果执行虚拟读取时记分板位未设置，则X形式的字符串将继续执行。 如果在执行虚拟机时设置了记分板位，则流水线停止，直到记分板位被清除，然后执行填充有生成的填充IOP（虚拟或NOP）的X形式字符串。 执行访问指令后，记分板位被清除。

公开(公告)号：US06442675B1

公开(公告)日：2002-08-27

申请号：US09363464

申请日：1999-07-29

申请人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le

发明人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le

IPC分类号： G06F938

CPC分类号： G06F9/30043 ,  G06F9/3017

摘要： A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in the string instruction. The operations that make up the string instruction are routed to parallel functional units and executed. The state-machine manipulates the size of the operations in the string instruction and whether or not the instructions need to be generated.

摘要翻译： 提供通用的可编程数据流状态机以接收关于特定字符串指令的信息。 字符串指令被解析为字符串指令中包含的所有操作。 构成字符串指令的操作被路由到并行功能单元并执行。 状态机在字符串指令中操作操作的大小以及是否需要生成指令。

公开(公告)号：US06286094B1

公开(公告)日：2001-09-04

申请号：US09263663

申请日：1999-03-05

申请人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le ,  Brian R. Konigsburg

发明人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le ,  Brian R. Konigsburg

IPC分类号： G06F930

CPC分类号： G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857

摘要： A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.

摘要翻译： 公开了一种用于确定处理系统中是否需要调度槽的方法和系统。 所述方法和系统包括多个预解码比特，以提供路由信息并利用所述预解码比特来允许指令被引导到特定解码时隙，并且在不检查指令的情况下服从调度约束。 该预编码系统方案的目的是为了提供关于指令分组的可能性最大的信息，而不增加使用该信息进行解码和组形成的逻辑的复杂性。 在优选实施例中，分析可以并行发出的每个指令的预解码位，并且为指令流内的每个可能的起始位置保留多路复用器控制。

公开(公告)号：US06345356B1

公开(公告)日：2002-02-05

申请号：US09354498

申请日：1999-07-16

申请人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le ,  Robert Greg McDonald

发明人： John Edward Derrick ,  Lee Evan Eisen ,  Hung Qui Le ,  Robert Greg McDonald

IPC分类号： G06F9312

CPC分类号： G06F9/3836 ,  G06F9/30018 ,  G06F9/30079 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard indicates the XER count is valid. After a read from a scoreboarded Special Purpose Register (SPR), No Operation—Internal Operations (NOP—IOPs) are inserted between write and read SPR IOPs to allow an ISU scoreboard mechanism to be activated before being tested by a read SPR IOP. A read-write-read sequence is utilized: a dummy read of the string count field from a scoreboarded SPR, writing that value back to the same SPR and then performing a read of the SPR once again. A predetermined number of dummy IOPs follow the initial dummy read to prevent the value of the string count field from being read too soon.

摘要翻译： 发出虚拟指令，其次是几组无操作（NOP）。 指令定序器单元（ISU）检测虚拟指令并停止流水线，直到记分板指示XER计数有效。 从记分板专用寄存器（SPR）读取后，在写入和读取SPR IOP之间插入无操作内部操作（NOP-IOP），以允许在读取SPR IOP测试之前激活ISU记分板机制。 使用读写读取序列：从记分板SPR中读取字符串计数字段，将该值写回相同的SPR，然后再次执行SPR的读取。 预定数量的虚拟IOP跟随初始伪读取，以防止字串计数字段的值被读取太快。

公开(公告)号：US06631463B1

公开(公告)日：2003-10-07

申请号：US09436103

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  John Anthony Moore ,  Kevin Franklin Reick ,  Edward John Silha

发明人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  John Anthony Moore ,  Kevin Franklin Reick ,  Edward John Silha

IPC分类号： G06F900

CPC分类号： G06F9/382 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3861

摘要： A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.

摘要翻译： 提出了一种用于在数据处理系统中的流水线处理器内修补有问题的指令的方法和装置。 获取多个指令，并且将多个指令与至少一个匹配条件进行匹配以生成匹配的指令。 匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。 可以使用伴随指令的匹配位通过指令流水线来标记匹配指令。 匹配的指令被替换为内部操作码或内部指令，使指令调度单元进行特殊的软件中断。 然后通过执行导致有问题的指令的期望的逻辑操作的一组指令来修补有问题的指令。

公开(公告)号：US06473850B1

公开(公告)日：2002-10-29

申请号：US09389197

申请日：1999-09-02

申请人： Hoichi Cheong ,  R. William Hay ,  James Allan Kahle ,  Hung Qui Le

发明人： Hoichi Cheong ,  R. William Hay ,  James Allan Kahle ,  Hung Qui Le

IPC分类号： G06F938

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3834

摘要： An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.

摘要翻译： ISYNC指令不会导致无条件地抛出推测分派或获取的指令（在ISYNC指令之后调度或取出的指令）。 本发明检测改变机器状态并需要上下文同步完成的任何指令的发生; 这些指令称为上下文同步所需指令。 当上下文同步所需指令完成时，本发明设置一个标志以注意该条件的发生。 当ISYNC指令完成时，如果上下文同步所需的标志是活动的，本发明引起冲洗并在ISYNC之后重新指定该指令。 然后，本发明重置上下文同步所需标志。 如果上下文同步所需的标志不是活动的，则本发明不产生刷新操作。

公开(公告)号：US06658555B1

公开(公告)日：2003-12-02

申请号：US09435077

申请日：1999-11-04

申请人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F930

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/3867 ,  G06F9/3885

摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

公开(公告)号：US06654869B1

公开(公告)日：2003-11-25

申请号：US09428399

申请日：1999-10-28

申请人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore

发明人： James Allan Kahle ,  Hung Qui Le ,  Charles Roberts Moore

IPC分类号： G06F500

CPC分类号： G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.

摘要翻译： 微处理器包括提取单元，指令分解单元以及调度和完成控制逻辑。 提取单元从指令高速缓存中检索一组指令。 指令解码单元接收所提取的指令集，并将该组指令组织到指令组中。 调度和完成逻辑将组标签分配给指令组，并将组标记记录在完成表的条目中，以跟踪包括指令组的指令的完成状态。 调度和控制逻辑可以在对应于每个指令组的完成表条目中记录单个指令地址。 优选地，单指令地址是指令组中的第一指令的指令地址。 响应于检测到指令组中的指令产生的异常，处理器可以刷新指令组。

公开(公告)号：US06543003B1

公开(公告)日：2003-04-01

申请号：US09436106

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

发明人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

IPC分类号： G06F1100

CPC分类号： G06F9/3885 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/1405

摘要： A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.

摘要翻译： 一种用于在具有多个执行单元的处理器中从挂起状态恢复的方法和装置。 执行监视以检测挂起状况。 响应于检测挂起状况，分配给多个执行单元的指令被刷新。

公开(公告)号：US06543002B1

公开(公告)日：2003-04-01

申请号：US09435066

申请日：1999-11-04

申请人： James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  Hung Qui Le ,  Kevin F. Reick ,  David James Shippy ,  Larry Edward Thatcher

IPC分类号： G06F1100

CPC分类号： G06F11/0721 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/0793 ,  G06F11/1405

摘要： A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch. The hang recovery unit then asserts a force reject signal to an execution unit to reject all instructions pending in the execution unit's pipeline and a flush signal to the execution unit that results in the processor flushing a set of instructions. The hang recovery unit then negates the force reject, stop completion, and stop dispatch signals to resume processor operation. In one embodiment, the recovery sequence includes entering a relaxed execution mode, such as a debug mode, a serial operation mode, or an in-order mode prior to resuming processor operation. In one embodiment, the processor advances a completion tag upon completing an instruction. In this manner the completion tag indicates the instruction that is next to complete. In one embodiment, the hang recovery sequence includes flushing the processor of an instruction set comprising all instructions with tag information greater than the completion tag. In another embodiment, all instructions with tag information greater than or equal to the completion tag are flushed.