公开(公告)号：US5448523A

公开(公告)日：1995-09-05

申请号：US306564

申请日：1994-09-15

申请人： James C. Lewis ,  Mark D. Bader

发明人： James C. Lewis ,  Mark D. Bader

IPC分类号： G06F12/08 ,  G11C15/04 ,  G11C15/00

CPC分类号： G06F12/0895

摘要： A cache TAG RAM (25) includes a TAG array (26), a small signal exclusive OR logic circuit (33, 34), a sense amplifier (36, 37), and another exclusive OR logic circuit (30, 31). A comparison of a stored TAG address to the input address signal is made by the small signal exclusive OR logic circuit (33, 34) to provide a hit signal very quickly. The stored TAG address that is lost during the exclusive OR operation is recovered by performing another exclusive OR on the match information and the input address signal. By using a small signal exclusive OR circuit to perform a comparison early, the hit signal can be generated very quickly.

摘要翻译： 缓存TAG RAM（25）包括TAG阵列（26），小信号异或逻辑电路（33,34），读出放大器（36,37）和另一异或逻辑电路（30,31）。 存储的TAG地址与输入地址信号的比较由小信号异或逻辑电路（33,34）进行，以非常快地提供命中信号。 通过对匹配信息和输入地址信号执行另一个异或来恢复在异或运算期间丢失的存储的TAG地址。 通过使用小信号异或电路来提前进行比较，可以非常快速地生成命中信号。

公开(公告)号：US5043945A

公开(公告)日：1991-08-27

申请号：US402733

申请日：1989-09-05

申请人： Mark D. Bader

发明人： Mark D. Bader

IPC分类号： G11C11/41 ,  G11C7/12

CPC分类号： G11C7/12

摘要： A memory for performing read cycles and write cycles has memory cells located at intersections of word lines and complementary bit line pairs. A row decoder receives a row address and drives a word line in response. In the read cycle, a column decoder decodes a column address to couple selected bit line pairs to global data lines for subsequent output. In the write cycle, write global data lines receive input data signals and couple them to selected bit line pairs for storage in memory cells located at intersections of the selected bit line pairs and enabled word lines. After the write cycle, equalization of bit lines is achieved partly by bit line loads coupled to each bit line, and partly by write data line loads located in the column decoder. Because the write data line loads are coupled to the bit lines after column decoding has taken place, the write data line loads can be shared by several bit line pairs. Thus, layout space is saved due to the sharing, and transistors in the write data line load can be made larger to improve the speed of the bit line equalization.

公开(公告)号：US5802586A

公开(公告)日：1998-09-01

申请号：US395225

申请日：1995-02-27

申请人： Kenneth W. Jones ,  Mark D. Bader ,  Arthur D. Kahlich

发明人： Kenneth W. Jones ,  Mark D. Bader ,  Arthur D. Kahlich

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0846 ,  G06F12/0879 ,  Y02B60/1225

摘要： A multiple-way, set associative cache memory (20) allows burst read and burst write operations to occur simultaneously on different columns within a memory block during a read-modify-write operation. This is accomplished by using a write column logic (47) and a read column logic (51) to delay write column decode signals by one clock cycle from the read column decode signals. When data is being burst into and out of the cache during the read-modify-write operation, the first read cycle from the cache array (40) occurs, and one clock cycle later, the first write cycle occurs. The first write cycle occurs during the same time interval as the second read cycle. This increases the speed of a read-modify-write operation, relaxes timing constraints on the read and write operations, while reducing the power consumption of the cache.

摘要翻译： 多重组合关联高速缓存存储器（20）允许在读 - 修改 - 写操作期间，在存储器块内的不同列上同时发生突发读和突发写操作。 这是通过使用写列逻辑（47）和读列逻辑（51）从读列解码信号延迟写列解码信号一个时钟周期来实现的。 当在读 - 修改 - 写入操作期间数据被突发进出高速缓存时，发生来自高速缓冲存储器阵列（40）的第一读取周期，并且在一个时钟周期之后，发生第一个写入周期。 第一个写周期在与第二个读周期相同的时间间隔内发生。 这增加了读 - 修改 - 写入操作的速度，同时降低了读取和写入操作的时序约束，同时降低了高速缓存的功耗。

公开(公告)号：US5473561A

公开(公告)日：1995-12-05

申请号：US306565

申请日：1994-09-15

申请人： Kenneth W. Jones ,  Mark D. Bader ,  Ketan B. Shah

发明人： Kenneth W. Jones ,  Mark D. Bader ,  Ketan B. Shah

IPC分类号： G06F12/08 ,  G11C15/00

CPC分类号： G11C15/00 ,  G06F12/0895

摘要： A cache TAG RAM (25) includes a reduction circuit (39) for comparing match signals from a plurality of exclusive OR logic circuits (33, 34) and provides a hit signal when all of the TAG address bits of a stored TAG address is the same as input address bits. The reduction circuit (39) provides a miss signal when any one or more of the bits of the stored TAG address is not the same as the corresponding bits of the input address bits. In one embodiment, the reduction circuit (39) uses a plurality of transistors (77, 78) coupled to a conductor (75) for discharging the conductor (75) if one of the exclusive OR logic circuits (33, 34) indicates a miss. In another embodiment, the reduction circuit (39") charges the conductor. The comparison can be made using signals having small signal swing at high speed, and a reference voltage is not needed for the comparison.

摘要翻译： 缓存TAG RAM（25）包括用于比较来自多个异或逻辑电路（33,34）的匹配信号的缩小电路（39），并且当所存储的TAG地址的所有TAG地址位是 与输入地址位相同。 当存储的TAG地址的任何一个或多个比特与输入地址比特的相应比特不同时，缩减电路（39）提供未命中信号。 在一个实施例中，如果异或逻辑电路（33,34）中的一个指示未命中，则还原电路（39）使用耦合到导体（75）的多个晶体管（77,78）来放电导体（75） 。 在另一个实施例中，还原电路（39“）对导体充电。 可以使用具有高速度的小信号摆幅的信号进行比较，并且不需要参考电压进行比较。

公开(公告)号：US5394026A

公开(公告)日：1995-02-28

申请号：US12496

申请日：1993-02-02

申请人： Ruey I. Yu ,  Mark D. Bader

发明人： Ruey I. Yu ,  Mark D. Bader

IPC分类号： G05F1/56 ,  G05F3/20 ,  H02M3/07 ,  H03K3/01

CPC分类号： G05F3/205

摘要： A substrate bias generating circuit (20) provides a substrate bias voltage to a substrate (50) of an integrated circuit. A voltage-to-current converter circuit (22) provides a constant current proportional to a bandgap generated reference voltage. P-channel transistors (34 and 35) then provide constant current sources for a voltage level sensing circuit (36) based on the bandgap generated reference voltage. The voltage level sensing circuit (36) monitors the level of the substrate bias voltage, and when the substrate bias voltage reaches a predetermined voltage level, provides a first control signal for activating an oscillator (47). A level converter (43) is provided to amplify, or level convert the first control signal for more reliable control of the oscillator. A substrate bias generating circuit (20) provides a precisely controlled substrate bias voltage to the substrate (50) that is independent of process, temperature, and power supply variations.

摘要翻译： 衬底偏置产生电路（20）向衬底（50）提供衬底偏置电压。 电压 - 电流转换器电路（22）提供与带隙产生的参考电压成比例的恒定电流。 然后，P沟道晶体管（34和35）基于带隙产生的参考电压为电压电平感测电路（36）提供恒定的电流源。 电压电平检测电路（36）监视衬底偏置电压的电平，并且当衬底偏置电压达到预定电压电平时，提供用于激活振荡器（47）的第一控制信号。 提供电平转换器（43）以放大或电平转换第一控制信号以更可靠地控制振荡器。 衬底偏置产生电路（20）向衬底（50）提供精确控制的衬底偏置电压，其独立于过程，温度和电源变化。

公开(公告)号：US4751680A

公开(公告)日：1988-06-14

申请号：US835681

申请日：1986-03-03

申请人： Karl L. Wang ,  Mark D. Bader ,  Peter H. Voss

发明人： Karl L. Wang ,  Mark D. Bader ,  Peter H. Voss

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/419

摘要： A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.

摘要翻译： 存储器具有位于位线对和字线的交点处的存储器单元。 在存储器的写入模式期间，位线处于最大电压分离。 为了在写入之后进行读取，必须先对位线进行均衡。 由于写入期间电压分压的程度，均衡位线可能会导致电源上的大峰值电流消耗。 通过响应于写入读取转换部分地对位线进行充电来减小该峰值电流，然后响应于行地址的转变将位线带到最终的均衡电压。 在写入读取转换与行地址转换同时发生的情况下，首先确保部分充电以确保降低的峰值电流。

公开(公告)号：USD422251S

公开(公告)日：2000-04-04

申请号：US83806

申请日：1998-02-18

申请人： Mark D. Bader ,  Bryan W. Delashaw ,  John F. Myers ,  Eric N. Tucker

设计人： Mark D. Bader ,  Bryan W. Delashaw ,  John F. Myers ,  Eric N. Tucker

公开(公告)号：US5268863A

公开(公告)日：1993-12-07

申请号：US909485

申请日：1992-07-06

申请人： Mark D. Bader ,  Kenneth W. Jones ,  Karl L. Wang ,  Ray Chang

发明人： Mark D. Bader ,  Kenneth W. Jones ,  Karl L. Wang ,  Ray Chang

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C8/18

摘要： A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

公开(公告)号：US4972374A

公开(公告)日：1990-11-20

申请号：US457646

申请日：1989-12-27

申请人： Karl L. Wang ,  Mark D. Bader

发明人： Karl L. Wang ,  Mark D. Bader

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C11/414 ,  G11C11/417

CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C7/1051

摘要： A memory uses address transition detection to reduce power consumption of the output amplification stage. The output amplification stage, which drives an output driver, has a series of stages which are disabled except when there is an address transition. When there is an address transition all of the stages are quickly enabled except the last stage. The last stage has its output clamped to an invalid state when the other stages are first enabled and then is enabled a predetermined time after the other stages are enabled. The output of the last stage is sensed by a detector. After the last stage has been enabled and is providing valid data, the detector detects that the output of the last stage is valid, and the series of stages are all disabled. The output driver latches the data and provides an output. The output stage is thus disabled and thus not wasting power except during the portion of a cycle when there is actual need for amplification. The stage at which valid data is detected, which is the last stage, is clamped and disabled at the beginning of the cycle to ensure that the detector does not detect, as being valid, data that is invalid.

摘要翻译： 存储器使用地址转换检测来降低输出放大级的功耗。 驱动输出驱动器的输出放大级具有禁用的一系列级，除非存在地址转换。 当有地址转换时，除了最后一个阶段之外，所有的阶段都被快速启用。 最后阶段的其他阶段首先启用后，其输出钳位到无效状态，然后在其他阶段启用后启用预定时间。 最后一级的输出由检测器检测。 在最后一个阶段启用并提供有效数据之后，检测器检测到最后一个阶段的输出是有效的，并且一系列的阶段都被禁用。 输出驱动器锁存数据并提供输出。 因此，当实际需要放大时，输出级被禁止，因此不会浪费功率，除了在循环的一部分期间。 检测到有效数据（最后一级）的阶段在周期开始时被钳位和禁用，以确保检测器没有检测到无效的数据。

公开(公告)号：US4689771A

公开(公告)日：1987-08-25

申请号：US835679

申请日：1986-03-03

申请人： Karl L. Wang ,  Mark D. Bader

发明人： Karl L. Wang ,  Mark D. Bader

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/41 ,  G11C11/40

CPC分类号： G11C7/22 ,  G11C7/10

摘要： A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.

摘要翻译： 存储器具有读取模式，其中从由列地址选择的位线对和数据被写入所选位线对的写入模式读取数据。 响应于列地址，所选位线对经由列解码器耦合到数据线对。 在从写入模式转换到读取模式时，列解码器在列禁止脉冲的持续时间内被禁止将所选数据线耦合到数据线对。 响应于写入转变脉冲或列转换脉冲或两者都产生列禁止脉冲。 响应于列地址的改变而产生列转换脉冲。 响应于写入读取转换而产生写入转换脉冲。