公开(公告)号：US5268863A

公开(公告)日：1993-12-07

申请号：US909485

申请日：1992-07-06

申请人： Mark D. Bader ,  Kenneth W. Jones ,  Karl L. Wang ,  Ray Chang

发明人： Mark D. Bader ,  Kenneth W. Jones ,  Karl L. Wang ,  Ray Chang

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C8/18

摘要： A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

公开(公告)号：US5477176A

公开(公告)日：1995-12-19

申请号：US253076

申请日：1994-06-02

申请人： Ray Chang ,  Lawrence F. Childs ,  Kenneth W. Jones ,  Donovan Raatz ,  Stephen Flannagan

发明人： Ray Chang ,  Lawrence F. Childs ,  Kenneth W. Jones ,  Donovan Raatz ,  Stephen Flannagan

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/10 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  G11C5/143 ,  G11C8/10 ,  H03K17/22 ,  H03K2017/226

摘要： A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

摘要翻译： 用于存储器（20）的上电复位电路（30）包括DC模型电路（39），NBIAS校验电路（64）和NAND逻辑门（71）。 在存储器（20）的上电时提供逻辑低电源复位信号，以在时钟电路（29）和行和列预解码器/锁存器（24,27）中建立初始条件。 当电源电压，带隙参考电压和偏置电压都达到其预定电压时，上电复位电路（30）提供逻辑高的上电复位信号。 以这种方式，确保上电复位电路（30）提供逻辑低功率复位信号，直到达到所有适当的电压电平。 此外，上电复位电路为等效于地址缓冲电路（79）的DC电路建模，用于补偿过程和温度变化。

公开(公告)号：US5440515A

公开(公告)日：1995-08-08

申请号：US207517

申请日：1994-03-08

申请人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

发明人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

IPC分类号： G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22

摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

摘要翻译： 延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。 仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步， 。 塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。 延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

公开(公告)号：US5384737A

公开(公告)日：1995-01-24

申请号：US207509

申请日：1994-03-08

申请人： Lawrence F. Childs ,  Kenneth W. Jones ,  Stephen T. Flannagan ,  Ray Chang

发明人： Lawrence F. Childs ,  Kenneth W. Jones ,  Stephen T. Flannagan ,  Ray Chang

IPC分类号： G11C7/10 ,  G11C29/14 ,  G11C13/00

CPC分类号： G11C29/14 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1072

摘要： A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).

摘要翻译： 流水线存储器（20）具有同步操作模式和异步操作模式。 存储器（20）包括用于在异步操作模式和同步操作模式之间电切换的输出寄存器（34）和输出使能寄存器（48）。 另外，在同步运行模式中，流水线的深度可以在三段管线和两级管线之间变化。 通过改变流水线的深度，存储器（20）可以使用更大的时钟频率范围来操作。 另外，可以改变操作频率以便于存储器（20）的测试和调试。

公开(公告)号：US5422848A

公开(公告)日：1995-06-06

申请号：US909484

申请日：1992-07-06

申请人： Kenneth W. Jones ,  Ray Chang

发明人： Kenneth W. Jones ,  Ray Chang

IPC分类号： G11C7/22 ,  H03K19/0175 ,  G11C7/00 ,  H03K19/094

CPC分类号： H03K19/017527 ,  G11C7/22

摘要： An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate level logic signals. The level converter receives the intermediate level logic signals and provides a CMOS level output signal. The NOR gate receives the CMOS level output signal, via the series connected inverters, at an input terminal after a predetermined delay. One of the intermediate level logic signals is also received by the NOR gate at a second input terminal. The CMOS level output signal is delayed for a predetermined time in a low-to-high transition, with no unwanted delay in a high-to-low transition.

摘要翻译： 具有单面延迟的ECL至CMOS缓冲器包括ECL逻辑门，电平转换器，多个串联连接的反相器和NOR门。 ECL逻辑门接收ECL电平输入信号，并提供互补的中间电平逻辑信号。 电平转换器接收中间电平逻辑信号并提供CMOS电平输出信号。 NOR门通过串联连接的反相器在预定的延迟之后的输入端接收CMOS电平输出信号。 中间电平逻辑信号之一也由第二输入端上的或非门接收。 CMOS电平输出信号在低到高的转换期间被延迟预定的时间，在高到低的转变中没有不期望的延迟。

公开(公告)号：US5258951A

公开(公告)日：1993-11-02

申请号：US919428

申请日：1992-07-27

申请人： Ruey J. Yu ,  Kenneth W. Jones ,  Ray Chang ,  Karl Wang

发明人： Ruey J. Yu ,  Kenneth W. Jones ,  Ray Chang ,  Karl Wang

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/062 ,  G11C7/1051

摘要： A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

摘要翻译： 存储器（20）具有读周期和写周期。 在读周期期间，对应于由所选存储单元提供的数据的差分数据信号叠加在第一共模电压上并提供给数据输出缓冲器（70-73）。 在写周期期间，读取全局数据线（61-62）上的差分数据信号在第二共模电压下相等，数据输出缓冲器（70-73）被禁用。 输出使能电路（74）在第一和第二共模电压之间提供输出使能信号。 当差分数据信号从第二共模电压转换到第一共模电压时，差分数据信号与输出使能信号交叉时，数据输出缓冲器（70-73）在读周期开始时使能。 以这种方式启用数据输出缓冲器（70-73）可大大放宽输出使能时序约束。

公开(公告)号：US5610543A

公开(公告)日：1997-03-11

申请号：US417155

申请日：1995-04-04

申请人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

发明人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

IPC分类号： G11C7/22 ,  H03L7/06 ,  H03K5/13

CPC分类号： G11C7/22

摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

摘要翻译： 延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。 仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步， 。 塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。 延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

公开(公告)号：US4991140A

公开(公告)日：1991-02-05

申请号：US460776

申请日：1990-01-04

申请人： Karl L. Wang ,  Ray Chang

发明人： Karl L. Wang ,  Ray Chang

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/22

摘要： An integrated circuit memory with improved di/dt control. The memory stores a plurality of data bits at intersections of word lines and bit line pairs. In response to a change in at least one of a plurality of address signals during a read cycle, first and second precharge signals are asserted, the second precharge signal asserted after the first precharge signal. An output buffer provides a data output signal at a voltage between a logic high and a logic low voltage in response to an assertion of the second precharge signal, and provides said data output signal corresponding to a voltage on an enabled bit line pair in response to a negation of the first precharge signal. Thus, the voltage on the data output signal changes less when the data bit is provided during the data period. The memory thus improves di/dt for a given access time, or conversely, allows reduced access time for a given di/dt.

摘要翻译： 具有改进di / dt控制的集成电路存储器。 存储器在字线和位线对的交叉处存储多个数据位。 响应于在读周期期间多个地址信号中的至少一个的变化，第一和第二预充电信号被断言，第二预充电信号在第一预充电信号之后被断言。 输出缓冲器响应于第二预充电信号的断言而在逻辑高电平和逻辑低电压之间的电压提供数据输出信号，并且响应于所述第二预充电信号提供对应于使能位线对上的电压的所述数据输出信号 第一个预充电信号的否定。 因此，在数据周期期间提供数据位时，数据输出信号上的电压变化较小。 因此，存储器在给定的访问时间内改善了di / dt，或者相反地，允许给定的di / dt减少访问时间。

公开(公告)号：US20090100275A1

公开(公告)日：2009-04-16

申请号：US11974699

申请日：2007-10-15

申请人： Ray Chang ,  David Ferguson

发明人： Ray Chang ,  David Ferguson

IPC分类号： G06F1/26

CPC分类号： H02J7/007 ,  G06F1/266 ,  H02J7/0052 ,  Y10T307/406

摘要： Methods and apparatus for dynamically adjusting the amount of power (or current) distributed to one or more connected devices via electrical interfaces. In one embodiment, the apparatus comprises a first module adapted to detect current drawn by a first set of ports, and a second module adapted to adjust the current provided to a second set of ports based on the detected current. The second module is also optionally adapted to distribute unreserved current among the devices according to an allocation protocol. In the exemplary context of a plurality of interconnected serial bus devices, the invention enables a device to draw more current than that required to be reserved for that device (such as to comply with a specification such as USB), yet without increasing the total amount of power which must be dedicated to the serial ports as a whole. Power supply efficiency may also be advantageously optimized.

摘要翻译： 用于通过电接口动态调整分配给一个或多个连接设备的功率（或电流）量的方法和装置。 在一个实施例中，该装置包括适于检测由第一组端口抽取的电流的第一模块，以及适于基于检测到的电流来调整提供给第二组端口的电流的第二模块。 第二模块还可选地适于根据分配协议在设备之间分配未保留的电流。 在多个互连的串行总线设备的示例性上下文中，本发明使得设备能够比不需要为该设备保留的电流（例如符合诸如USB的规范）绘制更多的电流，而不增加总量 必须专门用于整个串行端口的电源。 还可以有利地优化电源效率。

公开(公告)号：US07306487B1

公开(公告)日：2007-12-11

申请号：US11594243

申请日：2006-11-08

申请人： Ray Chang

发明人： Ray Chang

IPC分类号： H01R13/648

CPC分类号： H01R13/6461 ,  H01R13/6474 ,  H01R13/6593 ,  H01R24/64

摘要： A low crosstalk transmission connector includes a housing that houses a metal spring plate, a load bar, a terminal module and a locating frame, a cable organizer, which has an axle hole that receives a 8-wire cable and 8 wire grooves that separate the 8 insulated wires of the cable, and a metal shield that accommodates the cable organizer and has a bottom clamping plate and a top clamping plate respectively hooked on the bottom and top sides of the housing to ensure high steadity. The 4th and 6th metal contact terminals and the 1st, 2nd, 3rd, 5th, 7th and 8th metal contact terminals of the terminal module have the respective front contact portions curved in two reversed directions to reduce crosstalk noise, thereby improving transmission quality.

摘要翻译： 低串扰传输连接器包括容纳金属弹簧板，负载杆，端子模块和定位框架的壳体，电缆组织器，其具有容纳8线电缆的轴孔和8条线槽， 电缆的8根绝缘电线，以及容纳电缆组织器的金属屏蔽，并具有分别钩在外壳底部和顶部的底部夹紧板和顶部夹紧板，以确保高稳定性。 第4和第6和/或第4金属接触端子以及第1，第2，第3，第3 端子模块的第<！ - SIPO - >第五，第七和/或第八/第五金属接触端子具有相应的前接触部分弯曲成两个 反向方向以减少串扰噪声，从而提高传输质​​量。