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    METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY
    2.
    发明申请
    METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY 有权
    在非易失性静态随机访问存储器中实现复位功能的方法和装置

    公开(公告)号：US20120213027A1

    公开(公告)日：2012-08-23

    申请号：US13216546

    申请日：2011-08-24

    Applicant: James D. Allan ,  Jayant Ashokkumar

    Inventor： James D. Allan ,  Jayant Ashokkumar

    IPC: G11C5/14

    CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

    Abstract: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

    Abstract translation: 公开了一种用于复位半导体存储器的系统和方法。 本发明使用阵列复位电路来独立地驱动易失性存储器单元的高位或低位的位线，以将单个存储器单元或具有全0或全部1的阵列中的所有存储单元复位。

    Method and apparatus to create an erase disturb on a non-volatile static random access memory cell
    3.
    发明授权
    Method and apparatus to create an erase disturb on a non-volatile static random access memory cell 有权
    在非易失性静态随机存取存储器单元上产生擦除干扰的方法和装置

    公开(公告)号：US07505303B2

    公开(公告)日：2009-03-17

    申请号：US11644447

    申请日：2006-12-22

    Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan

    Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan

    IPC: G11C11/00

    CPC classification number: G11C16/3418 ,  G11C14/00 ,  G11C14/0063

    Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

    Abstract translation: 公开了一种用于干扰半导体存储器的非易失性部分中的擦除存储器位置结构的系统和方法。 本发明对半导体存储器的处于编程状态的非易失性部分的第一存储位置和处于擦除状态的半导体存储器的非易失性部分的第二存储器位置施加电压，以便 以使第一存储器位置被编程并且将第二存储器位置从编程状态转变到擦除状态。

    Method and apparatus to implement a reset function in a non-volatile static random access memory
    7.
    发明申请
    Method and apparatus to implement a reset function in a non-volatile static random access memory 审中-公开
    在非易失性静态随机存取存储器中实现复位功能的方法和装置

    公开(公告)号：US20080151654A1

    公开(公告)日：2008-06-26

    申请号：US11644165

    申请日：2006-12-22

    Applicant: James D. Allan ,  Jayant Ashokkumar

    Inventor： James D. Allan ,  Jayant Ashokkumar

    IPC: G11C7/20 ,  G11C7/12

    CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

    Abstract: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

    Abstract translation: 公开了一种用于复位半导体存储器的系统和方法。 本发明使用阵列复位电路来独立地驱动易失性存储器单元的高位或低位的位线，以将单个存储器单元或具有全0或全部1的阵列中的所有存储单元复位。

    Method and apparatus to create an erase disturb on a non-volatile static random access memory cell
    8.
    发明申请
    Method and apparatus to create an erase disturb on a non-volatile static random access memory cell 有权
    在非易失性静态随机存取存储器单元上产生擦除干扰的方法和装置

    公开(公告)号：US20080151643A1

    公开(公告)日：2008-06-26

    申请号：US11644447

    申请日：2006-12-22

    Applicant: Jayant Ashokkumar ,  David W. Still ,  James D. Allan

    Inventor： Jayant Ashokkumar ,  David W. Still ,  James D. Allan

    IPC: G11C16/00

    CPC classification number: G11C16/3418 ,  G11C14/00 ,  G11C14/0063

    Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

    Abstract translation: 公开了一种用于干扰半导体存储器的非易失性部分中的擦除存储器位置结构的系统和方法。 本发明对半导体存储器的处于编程状态的非易失性部分的第一存储位置和处于擦除状态的半导体存储器的非易失性部分的第二存储器位置施加电压，以便 以使第一存储器位置被编程并且将第二存储器位置从编程状态转变到擦除状态。

    Dram current control technique
    9.
    发明授权
    Dram current control technique 失效
    戏剧电流控制技术

    公开(公告)号：US4656612A

    公开(公告)日：1987-04-07

    申请号：US672907

    申请日：1984-11-19

    Applicant: James D. Allan

    Inventor： James D. Allan

    IPC: G11C11/409 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40

    CPC classification number: G11C11/4076

    Abstract: In a DRAM, current surges during sense and restore operations are compensated. Peak current through sense amplifiers is stabilized through initiation of the sense and restore operations during the chip active period and completion of the sense and restore operation during the chip precharge period. The delay between first and second sensing signals is controlled to be longer for those temperature and power supply conditions under which the chip is operating fastest. Correspondingly, the delay between first and second sensing signals is made shorter for those temperature and power supply conditions under which the chip is operating slowest. Overall peak current is limited to that drawn through small transistors used to begin turning on the sense amplifier. The duration of the second sensing signal is responsive to the temperature and power supply variation so it endures for an acceptable period in which to complete the sense and restore function. The second sensing signal timing is not determined by the first sensing signal.

    Abstract translation: 在DRAM中，感测和恢复操作期间的电流波动得到补偿。 通过感测放大器的峰值电流通过在芯片有效周期期间启动感测和恢复操作并且在芯片预充电期间完成感测和恢复操作来稳定。 对于芯片运行最快的温度和电源条件，第一和第二感测信号之间的延迟被控制得更长。 相应地，对于芯片运行最慢的温度和电源条件，第一和第二感测信号之间的延迟变短。 总峰值电流仅限于通过用于开始接通读出放大器的小型晶体管。 第二感测信号的持续时间响应于温度和电源变化，因此它可以忍受完成感测和恢复功能的可接受的时间段。 第二感测信号定时不由第一感测信号确定。

    Parallel test for asynchronous memory
    10.
    发明授权
    Parallel test for asynchronous memory 有权
    异步存储器的并行测试

    公开(公告)号：US06324107B1

    公开(公告)日：2001-11-27

    申请号：US09639454

    申请日：2000-08-15

    Applicant: James D. Allan ,  John J. Silver ,  Keith A. Ford

    Inventor： James D. Allan ,  John J. Silver ,  Keith A. Ford

    IPC: G11C700

    CPC classification number: G11C29/26

    Abstract: An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry. In a further embodiment, a plurality of cells of an asynchronous memory device may be read in parallel and an output signal indicative of a logical combination of logic states of the plurality of cells and a test signal at the speed of the slowest cell access time produced thereby.

    Abstract translation: 异步存储器件包括并行测试电路，其被配置为提供该器件的最慢位访问时间的量度。 并行测试电路可以包括被配置为从设备的多个单元接收逻辑信号并且提供指示多个单元的逻辑状态的第一输出信号的第一电路。 并行测试电路还可以包括被配置为接收第一输出信号并产生指示第一输出信号的逻辑状态的第二输出信号的第二电路。 并行测试电路可以是在存储器件的读取路径中使用的相同的电路，并且可以被配置为使得第二输出信号以最慢的位访问时间产生。 所测试的多个单元可以包括设备的冗余单元。 这种冗余对于测试电路是透明的。 在另一实施例中，可以并行地读取异步存储器件的多个单元，并且产生指示多个单元的逻辑状态的逻辑组合的输出信号和以最慢单元访问时间的速度产生的测试信号 从而。

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