公开(公告)号：US5185872A

公开(公告)日：1993-02-09

申请号：US486407

申请日：1990-02-28

申请人： James M. Arnold ,  Glenn J. Hinton ,  Frank S. Smith

发明人： James M. Arnold ,  Glenn J. Hinton ,  Frank S. Smith

IPC分类号： G06F9/22 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/325 ,  G06F9/3836 ,  G06F9/3838

摘要： A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory interface unit. Each unit connected to the scbok line can pull the line to indicate that it is busy. Each unit connected to the mem scbok line can pull the line to indicate that it is busy. The scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a register file operation. The mem scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a memory operation. Registers are checked concurrently with the issuing of an instruction. An instruction lacking any needed unit or a register is stopped in response to the asserted scbok line and reissued in the next cycle. Registers to be used by a multi-cycle instruction are marked busy for an instruction that is able to be executed. When a result for the multi-cycle instruction returns the registers previously marked busy are marked as not busy.

摘要翻译： 扫描线在数据处理系统中连接到寄存器文件和其他单元，例如执行单元和乘法/除法单元。 记忆体线连接到寄存器文件和其他单元，诸如指令单元和存储器接口单元。 连接到scbok线的每个单元可以拉线以指示它正忙。 连接到mem sckk线的每个单元可以拉线以指示它正忙。 sclok线表示当寄存器文件中忙于上一个指令的单元或寄存器不能用于寄存器文件操作的指令时。 mem sckk行表示当一个单元或寄存器文件中的一个寄存器正在忙于上一条指令时，不能用于存储器操作的指令。 寄存器与发出指令并发检查。 没有任何所需单元或寄存器的指令将停止响应断言的跳线，并在下一个周期重新发行。 多周期指令使用的寄存器将被标记为能够被执行的指令的忙。 当多周期指令的结果返回先前标记为忙的寄存器被标记为不忙时。

公开(公告)号：US5023844A

公开(公告)日：1991-06-11

申请号：US486408

申请日：1990-02-28

申请人： James M. Arnold ,  Glenn J. Hinton ,  Frank S. Smith

发明人： James M. Arnold ,  Glenn J. Hinton ,  Frank S. Smith

IPC分类号： G11C11/413 ,  G11C8/16 ,  G11C11/401

CPC分类号： G11C8/16

摘要： A random access memory cell in a register file having multiple independent read ports and multiple independent write ports that support parallel instruction execution. The RAM cell consumes low power and conforms to a tight layout pitch to meet the needs of the random access memory. A single column line is used, with the storage latch device (M 11, M 12) increased in size to provide for the noise margin loss with reference to the prior art two-column design. A single n-device (M 1) is attached to the opposite side of the cell latch (M 11, M 12) to clear the cell prior to writing zeros into the cell. The registers that are to be written are first cleared in the PH2 of the first clock cycle, with the data written in PH1 of the second clock cycle which writes the ones. The zero bits are also written at this time, but they find a cell that already is in the zero state, having been cleared in PH2 of the first clock cycle.

摘要翻译： 具有多个独立读端口的寄存器文件中的随机访问存储单元和支持并行指令执行的多个独立写端口。 RAM单元消耗低功率，符合紧凑的布局间距，以满足随机存取存储器的需要。 使用单列线，参考现有技术的两列设计，存储锁存装置（M 11，M 12）的尺寸增加以提供噪声容限损失。 在单元锁存器（M11，M12）的相对侧附加单个n器件（M 1），以在将零写入单元之前清除单元。 要写入的寄存器首先在第一个时钟周期的PH2中清零，其中写入第二个时钟周期的PH1中的数据写入。 此时也写入零位，但是它们发现已经处于零状态的单元，已在第一个时钟周期的PH2中清零。

公开(公告)号：US06378061B1

公开(公告)日：2002-04-23

申请号：US08150784

申请日：1993-11-12

申请人： Adrian Carbine ,  Glenn J. Hinton ,  Frank S. Smith

发明人： Adrian Carbine ,  Glenn J. Hinton ,  Frank S. Smith

IPC分类号： G06F930

CPC分类号： G06F9/3808 ,  G06F9/30054 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857

摘要： An instruction decoder that issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents (106) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes them to the machine bus (110) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers. This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100).

摘要翻译： 一种指令解码器，其通过在每个时钟周期期间以正确的信息驱动机器总线（110）来发布新的指令。 当执行记分操作时，该信息是从当前要执行的指令中提取的，或者从机器总线的先前内容（106）中循环回收的。 捕鼠器多路复用器（104）在操作码和操作数字段的几个来源之间进行选择，并通过多个转换级和多路复用器将它们路由到机器总线（110）。 使用哪个源的决定是基于指令提取单元中的指令队列当前正在查看什么样的指令。 指令队列通知指令解码器下一条指令是RISC操作（包括寄存器，存储器和/或分支指令）或作为微代码流的一部分的指令。 如果复杂的宏指令流正在进行，则可以通过别名寄存器访问其操作数。 这允许在执行一个微指令序列时，间接访问由宏代码指令的操作数指定的源或目标寄存器或宏指令的操作码。 这些混叠的操作数由宏指令混叠逻辑（100）维护。

公开(公告)号：US5428811A

公开(公告)日：1995-06-27

申请号：US233230

申请日：1994-04-26

申请人： Glenn J. Hinton ,  Frank S. Smith ,  Randy Steck

发明人： Glenn J. Hinton ,  Frank S. Smith ,  Randy Steck

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30141 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functional units capable of independently executing second microinstructions that take a single clock cycle to complete execution. The first and second microinstructions are issued by an instruction decoder. A microintruction bus (112) is connected to the instruction decoder, the register file, and to each of the first and second functional units. A REG interface and a destination bus (110) are also connected to the register file (6). A Scbok line (102) is connected between the instruction unit, the register file and to each one of the first and second functional units. The instruction decoder includes means for asserting the Scbok line to signal that a current microinstruction on the microintruction bus (112) is valid. Means in the register file disassert the Scbok signal upon the condition that any one register in the register file needed by the instruction on the microinstruction bus is busy. An EU write line (102) connected from one of the single cycle functional units to the multiple cycle functional units is asserted by one of the single cycle functional units upon the condition that the single cycle functional unit requests access to the destination bus. The multiple cycle functional units and single cycle functional units are connected to the REG interface and to the destination bus. Arbitration means (3) in each of the multiple cycle functional units respond to the EU write line and to the Scbok line to prevent access to the destination bus upon the condition that the EU write line and the Scbo k line are asserted.

摘要翻译： 微处理器寄存器文件（6）和能够独立地执行采取多个时钟周期以完成执行的第一微指令的多个第一功能单元之间的接口协议。 多个第二功能单元，其能够独立地执行采用单个时钟周期来完成执行的第二微指令。 第一和第二微指令由指令解码器发出。 微指令总线（112）连接到指令解码器，寄存器文件以及第一和第二功能单元中的每一个。 REG接口和目的地总线（110）也连接到寄存器文件（6）。 Scbok线（102）连接在指令单元，寄存器文件和第一和第二功能单元中的每一个之间。 指令解码器包括用于断言Scbok线以指示微注射总线（112）上的当前微指令有效的装置。 在寄存器文件中的意思是在微指令总线上的指令所需的寄存器文件中的任何一个寄存器正忙的条件下反转Scbok信号。 在单周期功能单元请求访问目的地总线的条件下，由单个周期功能单元之一连接到多个周期功能单元的欧盟写入线路（102）由单个周期功能单元之一断言。 多周期功能单元和单周期功能单元连接到REG接口和目标总线。 多个循环功能单元中的每一个中的仲裁装置（3）响应于EU写入线和Scbok线，以防止在EU写入线和Scbo k线被断言的条件下访问目的地总线。

公开(公告)号：USH1291H

公开(公告)日：1994-02-01

申请号：US630499

申请日：1990-12-20

申请人： Glenn J. Hinton ,  Frank S. Smith

发明人： Glenn J. Hinton ,  Frank S. Smith

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/30116 ,  G06F9/30138 ,  G06F9/30141 ,  G06F9/3885

摘要： A microprocessor having a memory coprocessor (10) connected to a MEM interface (16) and a register coprocessor (12) connected to a REG interface (14). The REG interface (14) and MEM interface (16) are connected to independent read and write ports of a register file (6). An Instruction Sequencer (7) also connected to an independent write port of the register file, to the REG interface and to the MEM interface. An Instruction Cache (9) supplies the instruction sequencer with at least two instruction words per clock (7). Single-cycle coprocessors (4) are connected to the REG interface (14) and a multiple-cycle coprocessors (2) are connected to the REG interface (14). An Address Generation Unit (3) is connected to the MEM interface (16) for executing load-effective-address instructions and address computations for loads and stores to thereby perform effective address calculations in parallel with instruction execution by the single-cycle coprocessor. The Instruction Sequencer (7) decodes incoming instruction words form the Cache, and issues up to three instructions on the REG interface (14), the MEM interface (16), and/or the branch logic within the Instruction Sequencer. The instruction sequencer includes means for detecting dependencies between the instructions to thereby prevent collisions between instructions. A local register cache (5) is provided connected to the MEM interface. The local register cache maintains a stack of multiple word local register sets, such that one each call the local registers are transferred from the register file (6) to the Local Register Cache (5) to thereby allocate the local registers in the register file for the called procedure and on a return the words are transferred back into the register file to the calling procedure.

公开(公告)号：US5459845A

公开(公告)日：1995-10-17

申请号：US336326

申请日：1994-11-08

申请人： Truong Nguyen ,  Frank S. Smith

发明人： Truong Nguyen ,  Frank S. Smith

IPC分类号： F02B75/02 ,  G06F9/32 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3867 ,  F02B2075/027

摘要： A microprocessor comprised of Instruction Fetch Unit (10), Instruction Decoder (12), Pipeline Sequencer (14), Register File (16), Multiply/Divider-Unit, Execution Unit, and REG coprocessors block (18) and instruction cache, Address Generation Unit, local register cache, and MEM coprocessors block (20). The Instruction Cache provides the Instruction fetch unit (10) with instructions every cycle. The instruction sequencer (IS) includes the Fetch Unit (IFU-10), the Instruction Decoder (ID-12) and the Pipeline Sequencer (PS-14). The instruction sequencer can decode and issue up to three instructions per clock. The pipe sequencer (14) employs a write back path to store snap shots of the state of the machine in pipe stages 1 and 2. This provides the way for branch guessing and the process switching to correct itself after issuing a wrong IP (in the case of the branch guessing), or a way to preserve the internal state of the machine at the time a context switching occurs in order to come back to the same condition it had left.

摘要翻译： 包括指令提取单元（10），指令解码器（12），流水线排序器（14），寄存器文件（16），乘法/分隔单元，执行单元和REG协处理器块（18）和指令高速缓冲存储器 生成单元，本地寄存器缓存和MEM协处理器块（20）。 指令缓存为每个周期提供指令提取单元（10）指令。 指令定序器（IS）包括读取单元（IFU-10），指令解码器（ID-12）和流水线排序器（PS-14）。 指令定序器可以每个时钟解码和发出多达三条指令。 管道排序器（14）采用回写路径来存储管道阶段1和2中机器状态的快照。这提供了分支猜测和过程切换的方式，以在发出错误的IP（在 分支猜测的情况），或在上下文切换发生时保持机器的内部状态的方式，以便回到与之相同的条件。

公开(公告)号：US5313605A

公开(公告)日：1994-05-17

申请号：US630534

申请日：1990-12-20

申请人： Scott Huck ,  Sunil Shenoy ,  Frank S. Smith

发明人： Scott Huck ,  Sunil Shenoy ,  Frank S. Smith

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00 ,  G06F15/78 ,  G11C15/00

CPC分类号： G06F12/0886 ,  G06F12/0802

摘要： A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected. The word positions within a row of the ROM are so ordered as to enable multiple words to be read out simultaneously regardless of what starting address is presented to the ROM. A second Y-mux (67) is provided between the cache RAM and the bus (19) for multiplexing the multiple words. The second Y-mux is controlled by at least one bit of the internally selected address. A multiplexer (74) is connected to the second Y-mux for shifting its input an appropriate amount according to bits of the starting address, such that the correct words are read out in the correct position.

摘要翻译： 分层存储器，其包括用于存储第一字的后备存储读/写存储器（18）和用于存储频繁使用的字的只读存储器RAM（60）。 缓冲存储器具有两个部分，一个高速缓存RAM（64）和一个由两个读取缓冲器组成的双字队列（62）。 缓存RAM被提供用于根据使用算法存储存储在后备存储器中的一些字的副本。 同时搜索ROM，队列缓冲区和高速缓存RAM，查看请求的字的地址是否在其中。 如果不是，则由后备存储器（18）提取（76），并将这些字写入读取缓冲器。 下一次该地址被呈现时，获取缓冲区被写入高速缓存并同时读出到总线。 在ROM和高速缓冲存储器RAM之间提供第一Y多路复用器（63），用于多路复用适当的ROM列以在选择内部微地址时直接驱动Cache RAM位线。 ROM的一行内的单词位置如此排序，以便能够同时读出多个单词，而不管哪个起始地址被呈现给ROM。 在高速缓冲存储器RAM和总线（19）之间提供第二Y多路复用器（67），用于复用多个字。 第二个Y-MUX由内部选择的地址的至少一位控制。 多路复用器（74）连接到第二Y-多路复用器，用于根据起始地址的位将其输入移位适当的量，使得在正确位置读出正确的字。

公开(公告)号：US5222244A

公开(公告)日：1993-06-22

申请号：US630497

申请日：1990-12-20

申请人： Adrian Carbine ,  Frank S. Smith

发明人： Adrian Carbine ,  Frank S. Smith

IPC分类号： G06F9/28 ,  G06F9/30 ,  G06F9/318 ,  G06F9/35

CPC分类号： G06F9/30192 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/35

摘要： An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.

摘要翻译： 指令解码器中的混叠逻辑（100）。 如果复杂的微指令流程正在进行，则可以通过别名寄存器访问操作数（116）。 这允许在执行一个微指令序列时，间接访问由宏代码指令的操作数指定的源或目标寄存器或宏指令的操作码。 这些混叠的操作数由寄存器（116）中的宏指令混叠逻辑（100）保持。 指令解码器在每个时钟周期期间通过驱动具有正确信息的机器总线（110）来发出新的指令。 捕鼠器多路复用器（104）在操作码和操作数字段的几个来源之间进行选择，并通过多个翻译阶段和多路复用器将它们路由到机器总线（110）。

公开(公告)号：US5454089A

公开(公告)日：1995-09-26

申请号：US141685

申请日：1993-10-26

申请人： Truong Nguyen ,  Frank S. Smith

发明人： Truong Nguyen ,  Frank S. Smith

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/324 ,  G06F9/322 ,  G06F9/3804

摘要： Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the selected word. A full adder (40) adds this displacement to the instruction pointer. The result is used as the branch address. The timing is such that a 1 clock lookahead is sufficient to hide this calculation from program execution. The branch register address is determined by the process ID and the macro mode state bit. The branch by pass mechanism causes the branch address to be driven from the calculation instead of a branch register. If a branch fail or scoreboard hit occurs, a write cancellation is generated to stop the current address calculation from being stored in a branch register. If a branch fail or scoreboard hit does not occur, then the current address calculation is stored in a branch register. If a branch bypass occurs, then the branch address is driven from the calculation. If a branch bypass does not occur, then the branch address is driven from the branch register.

摘要翻译： 逻辑检查来自指令获取单元的信号以确定下一条指令是否是分支。 多路复用器选择4个指令字中的一个。 MACRO [0：3]和所选词的位移。 全加器（40）将该位移加到指令指针。 结果用作分支地址。 时间是这样的，1秒钟的前瞻就足以将程序执行隐藏起来。 分支寄存器地址由进程ID和宏模式状态位决定。 通过分支机制使分支地址从计算而不是分支寄存器驱动。 如果发生分支失败或记分牌命中，则产生写入取消，以将当前地址计算停止存储在分支寄存器中。 如果分支失败或记分板命中不发生，则当前地址计算存储在分支寄存器中。 如果发生分支旁路，则从计算中驱动分支地址。 如果不发生分支旁路，则从分支寄存器驱动分支地址。