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公开(公告)号：US06590433B2
公开(公告)日：2003-07-08
申请号：US09733445
申请日：2000-12-08
IPC分类号： H03B100
CPC分类号： H03K19/1736 , H03K19/018592
摘要： A bi-directional buffer includes the capability to turn the current mirror off when the bi-directional buffer is in the receive mode and quickly turn the current mirror on when the bi-directional buffer goes into the transmit mode. This is accomplished in part by a pair of switches included in the current mirror, which are controlled by enable signals. The switches are configured such that the output transistor of the current mirror is turned on when the bi-directional buffer is in the transmit mode, and turned off when the bi-directional buffer is in the receive mode. Further, a pull up circuit may be added to the current mirror to more quickly bring the gate of the output transistor of the current mirror to its conduction threshold voltage.
摘要翻译： 双向缓冲器包括当双向缓冲器处于接收模式时关闭当前镜像的能力，并且当双向缓冲器进入发送模式时，快速打开电流镜。 这部分由包括在电流镜中的一对开关实现，其由使能信号控制。 开关被配置为使得当双向缓冲器处于发送模式时电流镜的输出晶体管导通，并且当双向缓冲器处于接收模式时，该开关被断开。 此外，可以向电流镜添加上拉电路，以更快速地将电流镜的输出晶体管的栅极导通到其导通阈值电压。
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2.发明申请公开(公告)号：US20120155495A1
公开(公告)日：2012-06-21
申请号：US13405053
申请日：2012-02-24
申请人： James T. Clee , Deepak Mital , Robert J. Munoz
发明人： James T. Clee , Deepak Mital , Robert J. Munoz
IPC分类号： H04J3/24
CPC分类号： G06F15/167 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide for processing received data packets into packet reassemblies for transmission as output packets of a network processor. A packet assembler determines an associated packet reassembly of data portions and enqueues an identifier for each data portion in an input queue corresponding to the packet reassembly associated with the data portion. A state data entry corresponding to each packet reassembly identifies whether the packet reassembly is actively processed by the packet assembler. Iteratively, until an eligible data portion is selected, the packet assembler selects a given data portion from a non-empty input queue for processing and determines if the selected data portion corresponds to a reassembly that is actively processed. If the reassembly is active, the packet assembler sets the selected data portion as ineligible for selection. Otherwise, the packet assembler selects the data portion for processing and modifies the packet reassembly based on the selected data portion.
摘要翻译： 描述的实施例提供将接收到的数据分组处理成分组重新组装以便作为网络处理器的输出分组传输。 分组汇编器确定数据部分的相关联的分组重组，并且对与输入数据部分相关联的分组重新组合对应的输入队列中的每个数据部分进行排队。 与每个分组重组相对应的状态数据条目标识分组重组是否由分组汇编器主动处理。 迭代地，直到选择合格的数据部分为止，分组汇编器从非空输入队列中选择给定的数据部分进行处理，并确定所选择的数据部分是否对应于主动处理的重组。 如果重新组装有效，则分组汇编器将所选择的数据部分设置为不合格以供选择。 否则，分组组合器基于所选择的数据部分选择数据部分进行处理和修改分组重组。
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公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
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4.发明授权公开(公告)号：US08761204B2
公开(公告)日：2014-06-24
申请号：US13405053
申请日：2012-02-24
申请人： James T. Clee , Deepak Mital , Robert J. Munoz
发明人： James T. Clee , Deepak Mital , Robert J. Munoz
IPC分类号： H04J3/24
CPC分类号： G06F15/167 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide for processing received data packets into packet reassemblies for transmission as output packets of a network processor. A packet assembler determines an associated packet reassembly of data portions and enqueues an identifier for each data portion in an input queue corresponding to the packet reassembly associated with the data portion. A state data entry corresponding to each packet reassembly identifies whether the packet reassembly is actively processed by the packet assembler. Iteratively, until an eligible data portion is selected, the packet assembler selects a given data portion from a non-empty input queue for processing and determines if the selected data portion corresponds to a reassembly that is actively processed. If the reassembly is active, the packet assembler sets the selected data portion as ineligible for selection. Otherwise, the packet assembler selects the data portion for processing and modifies the packet reassembly based on the selected data portion.
摘要翻译： 描述的实施例提供将接收到的数据分组处理成分组重新组装以便作为网络处理器的输出分组传输。 分组汇编器确定数据部分的相关联的分组重组，并且对与输入数据部分相关联的分组重新组合对应的输入队列中的每个数据部分进行排队。 与每个分组重组相对应的状态数据条目标识分组重组是否由分组汇编器主动处理。 迭代地，直到选择合格的数据部分为止，分组汇编器从非空输入队列中选择给定的数据部分进行处理，并确定所选数据部分是否对应于主动处理的重组。 如果重新组装有效，则分组汇编器将所选择的数据部分设置为不合格以供选择。 否则，分组组合器基于所选择的数据部分选择数据部分进行处理和修改分组重组。
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