摘要:
Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
摘要:
Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.
摘要:
Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.
摘要:
Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.
摘要:
Described embodiments provide a method of updating configuration data of a network processor having one or more processing modules and a shared memory. A control processor of the network processor writes updated configuration data to the shared memory and sends a configuration update request to a configuration manager. The configuration update request corresponds to the updated configuration data. The configuration manager determines whether the configuration update request corresponds to settings of a given one of the processing modules. If the configuration update request corresponds to settings of a given one of the one or more processing modules, the configuration manager, sends one or more configuration operations to a destination one of the processing modules corresponding to the configuration update request and updated configuration data. The destination processing module updates one or more register values corresponding to configuration settings of the processing module with the corresponding updated configuration data.
摘要:
Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units.
摘要:
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.
摘要:
Described embodiments provide a method of updating configuration data of a network processor having one or more processing modules and a shared memory. A control processor of the network processor writes updated configuration data to the shared memory and sends a configuration update request to a configuration manager. The configuration update request corresponds to the updated configuration data. The configuration manager determines whether the configuration update request corresponds to settings of a given one of the processing modules. If the configuration update request corresponds to settings of a given one of the one or more processing modules, the configuration manager, sends one or more configuration operations to a destination one of the processing modules corresponding to the configuration update request and updated configuration data. The destination processing module updates one or more register values corresponding to configuration settings of the processing module with the corresponding updated configuration data.
摘要:
Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.
摘要:
Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units.