EXCEPTION DETECTION AND THREAD RESCHEDULING IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR
    3.
    发明申请
    EXCEPTION DETECTION AND THREAD RESCHEDULING IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR 有权
    多核心多线程处理器中的异常检测和螺纹延迟

    公开(公告)号:US20110225589A1

    公开(公告)日:2011-09-15

    申请号:US13046726

    申请日:2011-03-12

    IPC分类号: G06F9/46 G06F13/14

    摘要: Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.

    摘要翻译: 描述的实施例提供具有多个处理模块的网络处理器的分组分类器。 调度器针对与每个接收的分组相对应的由网络处理器生成的每个任务生成上下文的线程。 线程对应于应用于相应分组的指令的顺序。 多线程指令引擎处理指令的线程。 功能总线接口检查从多线程指令引擎接收的指令是否存在一个或多个异常情况。 如果功能总线接口检测到异常,则功能总线接口向调度程序和多线程指令引擎报告异常。 调度器对与具有用于在多线程指令引擎中进行处理的异常的指令相对应的线程进行重新调度。 否则,功能总线接口向网络处理器的相应目标处理模块提供指令。

    Exception detection and thread rescheduling in a multi-core, multi-thread network processor
    4.
    发明授权
    Exception detection and thread rescheduling in a multi-core, multi-thread network processor 有权
    多核,多线程网络处理器中的异常检测和线程重新调度

    公开(公告)号:US08537832B2

    公开(公告)日:2013-09-17

    申请号:US13046726

    申请日:2011-03-12

    IPC分类号: H04L12/28

    摘要: Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.

    摘要翻译: 描述的实施例提供具有多个处理模块的网络处理器的分组分类器。 调度器针对与每个接收的分组相对应的由网络处理器生成的每个任务生成上下文的线程。 线程对应于应用于相应分组的指令的顺序。 多线程指令引擎处理指令的线程。 功能总线接口检查从多线程指令引擎接收的指令是否存在一个或多个异常情况。 如果功能总线接口检测到异常,则功能总线接口向调度程序和多线程指令引擎报告异常。 调度器对与具有用于在多线程指令引擎中进行处理的异常的指令相对应的线程进行重新调度。 否则,功能总线接口向网络处理器的相应目标处理模块提供指令。

    DYNAMIC CONFIGURATION OF PROCESSING MODULES IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
    5.
    发明申请
    DYNAMIC CONFIGURATION OF PROCESSING MODULES IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
    网络通信处理器架构中处理模块的动态配置

    公开(公告)号:US20110289179A1

    公开(公告)日:2011-11-24

    申请号:US13192140

    申请日:2011-07-27

    IPC分类号: G06F15/167

    摘要: Described embodiments provide a method of updating configuration data of a network processor having one or more processing modules and a shared memory. A control processor of the network processor writes updated configuration data to the shared memory and sends a configuration update request to a configuration manager. The configuration update request corresponds to the updated configuration data. The configuration manager determines whether the configuration update request corresponds to settings of a given one of the processing modules. If the configuration update request corresponds to settings of a given one of the one or more processing modules, the configuration manager, sends one or more configuration operations to a destination one of the processing modules corresponding to the configuration update request and updated configuration data. The destination processing module updates one or more register values corresponding to configuration settings of the processing module with the corresponding updated configuration data.

    摘要翻译: 描述的实施例提供了一种更新具有一个或多个处理模块和共享存储器的网络处理器的配置数据的方法。 网络处理器的控制处理器将更新的配置数据写入共享存储器,并将配置更新请求发送给配置管理器。 配置更新请求对应于更新的配置数据。 配置管理器确定配置更新请求是否对应于给定的一个处理模块的设置。 如果配置更新请求对应于一个或多个处理模块中给定的一个处理模块的设置,则配置管理器向对应于配置更新请求和更新的配置数据的处理模块之一发送一个或多个配置操作。 目的地处理模块使用相应的更新的配置数据更新与处理模块的配置设置相对应的一个或多个寄存器值。

    CONCURRENT, COHERENT CACHE ACCESS FOR MULTIPLE THREADS IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR
    6.
    发明申请
    CONCURRENT, COHERENT CACHE ACCESS FOR MULTIPLE THREADS IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR 有权
    多核,多线程网络处理器中的多路径的相干缓存访问

    公开(公告)号:US20110225372A1

    公开(公告)日:2011-09-15

    申请号:US12976228

    申请日:2010-12-22

    申请人: Jerry Pirog

    发明人: Jerry Pirog

    IPC分类号: G06F12/08

    摘要: Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units.

    摘要翻译: 描述的实施例提供具有多个处理模块的网络处理器的分组分类器。 调度器针对与每个接收的分组相对应的由网络处理器生成的每个任务生成上下文的线程。 线程对应于应用于相应分组的指令的顺序。 多线程指令引擎处理指令的线程。 状态引擎对从多线程指令引擎接收的指令进行操作,指令包括对状态引擎的本地高速缓存的高速缓存访​​问请求。 状态引擎的高速缓存行入口管理器在对应于高速缓存访​​问请求的数据的逻辑索引值和存储在本地高速缓存中的数据的物理地址之间进行转换。 高速缓存行入口管理器管理本地高速缓存的数据一致性,并且允许对于非重叠数据单元的给定高速缓存数据线的一个或多个并发高速缓存访​​问请求。

    Thread synchronization in a multi-thread network communications processor architecture
    7.
    发明授权
    Thread synchronization in a multi-thread network communications processor architecture 有权
    线程同步在多线程网络通信处理器架构中

    公开(公告)号:US08910171B2

    公开(公告)日:2014-12-09

    申请号:US12974477

    申请日:2010-12-21

    摘要: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.

    摘要翻译: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器,用于从网络处理器的多个处理模块生成与分组分类器接收到的任务相对应的上下文。 多线程指令引擎处理指令的线程,每个指令线程与从调度器接收的上下文相对应。 线程状态管理器维护具有N个条目的线程状态表以跟踪多达N个活动线程。 每个状态条目包括有效的状态指示符,序列值和线程指示符。 序列计数器产生每个线程的序列值,并且当线程的处理开始时递增,并且在线程完成时由多线程指令引擎递减。 指令由多线程指令引擎以线程启动的顺序进行处理。

    Dynamic configuration of processing modules in a network communications processor architecture
    8.
    发明授权
    Dynamic configuration of processing modules in a network communications processor architecture 有权
    处理模块在网络通信处理器架构中的动态配置

    公开(公告)号:US09444757B2

    公开(公告)日:2016-09-13

    申请号:US13192140

    申请日:2011-07-27

    摘要: Described embodiments provide a method of updating configuration data of a network processor having one or more processing modules and a shared memory. A control processor of the network processor writes updated configuration data to the shared memory and sends a configuration update request to a configuration manager. The configuration update request corresponds to the updated configuration data. The configuration manager determines whether the configuration update request corresponds to settings of a given one of the processing modules. If the configuration update request corresponds to settings of a given one of the one or more processing modules, the configuration manager, sends one or more configuration operations to a destination one of the processing modules corresponding to the configuration update request and updated configuration data. The destination processing module updates one or more register values corresponding to configuration settings of the processing module with the corresponding updated configuration data.

    摘要翻译: 描述的实施例提供了一种更新具有一个或多个处理模块和共享存储器的网络处理器的配置数据的方法。 网络处理器的控制处理器将更新的配置数据写入共享存储器,并将配置更新请求发送给配置管理器。 配置更新请求对应于更新的配置数据。 配置管理器确定配置更新请求是否对应于给定的一个处理模块的设置。 如果配置更新请求对应于一个或多个处理模块中给定的一个处理模块的设置,则配置管理器向对应于配置更新请求和更新的配置数据的处理模块之一发送一个或多个配置操作。 目的地处理模块使用相应的更新的配置数据更新与处理模块的配置设置相对应的一个或多个寄存器值。

    Packet assembly module for multi-core, multi-thread network processors
    9.
    发明授权
    Packet assembly module for multi-core, multi-thread network processors 有权
    分组汇编模块,用于多核,多线程网络处理器

    公开(公告)号:US08943507B2

    公开(公告)日:2015-01-27

    申请号:US12971742

    申请日:2010-12-17

    IPC分类号: G06F7/68 G06F15/167 G06F9/38

    摘要: Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.

    摘要翻译: 所描述的实施例提供了一种用于网络处理器的分组组装器。 网络处理器包括用于将接收到的分组处理成一个或多个处理分组部分的多个处理模块。 网络处理器的共享系统存储器接收对应于分组组件的处理分组部分。 每个分组组件都具有相关联的任务。 分组组合处理器根据来自与分组组合相关联的任务的指令,从处理分组部分为每个分组组合构建输出分组。 分组组合处理器基于来自与相应分组组合相关联的任务的指令来协调从系统存储器读取的每个输出分组的处理分组部分的存储。

    Concurrent, coherent cache access for multiple threads in a multi-core, multi-thread network processor
    10.
    发明授权
    Concurrent, coherent cache access for multiple threads in a multi-core, multi-thread network processor 有权
    多核,多线程网络处理器中多线程的并发缓存访问

    公开(公告)号:US08935483B2

    公开(公告)日:2015-01-13

    申请号:US12976228

    申请日:2010-12-22

    申请人: Jerry Pirog

    发明人: Jerry Pirog

    摘要: Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units.

    摘要翻译: 描述的实施例提供具有多个处理模块的网络处理器的分组分类器。 调度器针对与每个接收的分组相对应的由网络处理器生成的每个任务生成上下文的线程。 线程对应于应用于相应分组的指令的顺序。 多线程指令引擎处理指令的线程。 状态引擎对从多线程指令引擎接收的指令进行操作,该指令包括对状态引擎的本地高速缓存的高速缓存访​​问请求。 状态引擎的高速缓存行入口管理器在对应于高速缓存访​​问请求的数据的逻辑索引值和存储在本地高速缓存中的数据的物理地址之间进行转换。 高速缓存行入口管理器管理本地高速缓存的数据一致性,并且允许对于非重叠数据单元的给定高速缓存数据线的一个或多个并发高速缓存访​​问请求。