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公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
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2.发明授权Instruction-set architecture for programmable cyclic redundancy check (CRC) computations 有权用于可编程循环冗余校验（CRC）计算的指令集架构公开(公告)号：US08464125B2
公开(公告)日：2013-06-11
申请号：US12653249
申请日：2009-12-10
申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
发明人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
IPC分类号： H03M13/00
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译： 提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。 灵活的CRC指令使用可编程的n位多项式来执行CRC操作。 通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。
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3.发明授权公开(公告)号：US08417943B2
公开(公告)日：2013-04-09
申请号：US13270532
申请日：2011-10-11
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.
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4.发明授权Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor 有权用于在可编程网络处理器中调度由密码算法核心执行的命令的处理的方法和装置公开(公告)号：US08065678B2
公开(公告)日：2011-11-22
申请号：US12380575
申请日：2009-02-27
申请人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.
摘要翻译： 一种用于通过网络处理器中的多个加密算法核心调度命令处理的方法和装置。
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5.发明申请Instruction-set architecture for programmable cyclic redundancy check (CRC) computations 有权用于可编程循环冗余校验（CRC）计算的指令集架构公开(公告)号：US20110145683A1
公开(公告)日：2011-06-16
申请号：US12653249
申请日：2009-12-10
申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
发明人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译： 提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。 灵活的CRC指令使用可编程的n位多项式来执行CRC操作。 通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。
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6.发明申请METHOD AND APPARATUS FOR SCHEDULING THE PROCESSING OF COMMANDS FOR EXECUTION BY CRYPTOGRAPHIC ALGORITHM CORES IN A PROGRAMMABLE NETWORK PROCESSOR 审中-公开用于调度在可编程网络处理器中执行编码算法的命令的处理方法和装置公开(公告)号：US20120060159A1
公开(公告)日：2012-03-08
申请号：US13293807
申请日：2011-11-10
申请人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.
摘要翻译： 一种用于通过网络处理器中的多个加密算法核心调度命令处理的方法和装置。
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公开(公告)号：US20080075278A1
公开(公告)日：2008-03-27
申请号：US11534330
申请日：2006-09-22
IPC分类号： H04L9/30
CPC分类号： H04L9/0618 , G09C1/00 , H04L2209/122
摘要： Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.
摘要翻译： 这里描述了覆盖和合并任意数目的等效大小和结构的表的技术。 可以将表中相似的比特或模式设置为表示相应的逻辑“0”或“1”的电压值。 表中不同的位可以连接到表选择信号的值或其反相。
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公开(公告)号：US20140189212A1
公开(公告)日：2014-07-03
申请号：US13976262
申请日：2011-09-30
申请人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
发明人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
CPC分类号： G06F13/28 , G06F3/061 , G06F3/0613 , G06F3/0619 , G06F3/0626 , G06F3/064 , G06F3/0646 , G06F3/065 , G06F3/0659 , G06F3/0688 , G06F3/0689 , G06F11/1068 , G06F12/0866 , G06F13/102 , G06F13/1668 , G06F13/4068 , G06F13/4282 , G06F2212/262 , G06F2213/0026 , G06F2213/0032
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.
摘要翻译： 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。
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9.发明授权Method and apparatus for performing an authentication after cipher operation in a network processor 有权在网络处理器中进行密码操作之后进行认证的方法和装置公开(公告)号：US08041945B2
公开(公告)日：2011-10-18
申请号：US12455038
申请日：2009-05-27
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.
摘要翻译： 描述了一种方法和装置，用于通过具有对网络数据分组内的数据进行操作的密码处理核和认证处理核的网络处理器来处理网络数据分组，以便提供网络数据的一次通过加密和认证处理 数据包
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公开(公告)号：US09417821B2
公开(公告)日：2016-08-16
申请号：US13976262
申请日：2011-09-30
申请人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
发明人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
CPC分类号： G06F13/28 , G06F3/061 , G06F3/0613 , G06F3/0619 , G06F3/0626 , G06F3/064 , G06F3/0646 , G06F3/065 , G06F3/0659 , G06F3/0688 , G06F3/0689 , G06F11/1068 , G06F12/0866 , G06F13/102 , G06F13/1668 , G06F13/4068 , G06F13/4282 , G06F2212/262 , G06F2213/0026 , G06F2213/0032
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.
摘要翻译： 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。
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