公开(公告)号：US07636408B2

公开(公告)日：2009-12-22

申请号：US11445781

申请日：2006-06-01

申请人： Jason H. Bau ,  Drew G. Doblar ,  Gabriel C. Risk

发明人： Jason H. Bau ,  Drew G. Doblar ,  Gabriel C. Risk

IPC分类号： H04L7/00

CPC分类号： H04L25/03038 ,  H04L7/0004 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03057 ,  H04L25/03885 ,  H04L2025/03656 ,  H04L2025/03751 ,  H04L2025/03764

摘要： An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.

摘要翻译： 公开了一种用于从源同步输入数据流恢复时钟和数据流的装置和方法。 该装置包括滤波器，判决反馈均衡器（DFE），相位误差检测器和时钟发生器。 输入数据流耦合到滤波器和DFE。 DFE将输入数据流同步到时钟发生器产生的时钟。 滤波器输出和DFE输出各自耦合到相位误差检测器。 在初始化期间，相位误差检测器基于滤波器输出的一个或多个相位误差估计和在稳态运行期间向时钟发生器传送相位误差，相位误差检测器将相位误差传送到时钟 基于DFE输出的一个或多个相位误差估计的发生器。 DFE的输出包括恢复的数据流。

公开(公告)号：US20070280343A1

公开(公告)日：2007-12-06

申请号：US11445781

申请日：2006-06-01

申请人： Jason H. Bau ,  Drew G. Doblar ,  Gabriel C. Risk

发明人： Jason H. Bau ,  Drew G. Doblar ,  Gabriel C. Risk

IPC分类号： H03H7/30

CPC分类号： H04L25/03038 ,  H04L7/0004 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03057 ,  H04L25/03885 ,  H04L2025/03656 ,  H04L2025/03751 ,  H04L2025/03764

摘要： An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.

摘要翻译： 公开了一种用于从源同步输入数据流恢复时钟和数据流的装置和方法。 该装置包括滤波器，判决反馈均衡器（DFE），相位误差检测器和时钟发生器。 输入数据流耦合到滤波器和DFE。 DFE将输入数据流同步到时钟发生器产生的时钟。 滤波器输出和DFE输出各自耦合到相位误差检测器。 在初始化期间，相位误差检测器基于滤波器输出的一个或多个相位误差估计和在稳态运行期间向时钟发生器传送相位误差，相位误差检测器将相位误差传送到时钟 基于DFE输出的一个或多个相位误差估计的发生器。 DFE的输出包括恢复的数据流。

公开(公告)号：US20100158177A1

公开(公告)日：2010-06-24

申请号：US12342825

申请日：2008-12-23

申请人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

发明人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

IPC分类号： H04L7/00

CPC分类号： H04L7/0062 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/10

摘要： A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.

摘要翻译： 实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。 一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。

公开(公告)号：US07409491B2

公开(公告)日：2008-08-05

申请号：US11302728

申请日：2005-12-14

申请人： Drew G. Doblar ,  Gabriel C. Risk ,  Chung-Hsiao R. Wu

发明人： Drew G. Doblar ,  Gabriel C. Risk ,  Chung-Hsiao R. Wu

IPC分类号： G06F13/14

CPC分类号： G06F13/1684 ,  G11C5/00

摘要： A memory system comprising memory modules including memory chips stacked with switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a stacked switching circuit detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple stacked switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data. Switching circuits may be coupled to a stacked memory chip via a flexible interconnect, and may also be manufactured side by side with a corresponding memory chip on a flexible circuit board.

摘要翻译： 一种包括存储器模块的存储器系统，包括堆叠有开关电路的存储器芯片。 耦合到存储器模块的存储器控​​制器被配置为启动存储器访问。 当堆叠的开关电路检测到存储器访问时，如果访问不被引导到接收存储器模块的存储器芯片，则切换电路将访问路由到另一个存储器模块，或者如果访问被定向到存储器芯片则在本地处理访问 的接收存储器模块。 存储器控制器和存储器模块通过双向串行链路耦合。 每个存储器模块可以包括多个堆叠的开关电路，每个存储器模块可以耦合到比存储器模块内的所有存储器芯片少。 开关电路还包括被配置为在传送到存储器芯片之前对数据进行反序列化的电路，以及在发送所接收的数据之前串行从DRAM芯片接收的数据。 开关电路可以通过柔性互连耦合到堆叠的存储器芯片，并且还可以与柔性电路板上的对应的存储器芯片并排地制造。

公开(公告)号：US07224638B1

公开(公告)日：2007-05-29

申请号：US11304166

申请日：2005-12-15

申请人： Gabriel C. Risk ,  Leandro A. Chua, Jr. ,  Drew G. Doblar

发明人： Gabriel C. Risk ,  Leandro A. Chua, Jr. ,  Drew G. Doblar

IPC分类号： G11C8/00

CPC分类号： G11C7/20 ,  G11C7/22 ,  G11C7/222

摘要： A data communications system is disclosed. The data communications system comprises two clock domains. A first clock domain includes a transmitter and a first clock signal. A second clock domain includes a receiver and a second clock signal. The transmitter conveys the first clock signal and a data signal to the receiver. The receiver: (a) counts a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal; (b) maintains a first count of the number of transitions of the second clock signal; (c) samples the data signal and maintains a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value; and (d) samples the data signal and resets the second count in response to detecting the second count equals a second pre-determined value.

摘要翻译： 公开了一种数据通信系统。 数据通信系统包括两个时钟域。 第一时钟域包括发射机和第一时钟信号。 第二时钟域包括接收机和第二时钟信号。 发射机将第一时钟信号和数据信号传送到接收机。 接收机：（a）响应于检测到第一时钟信号的转变，对第二时钟信号的第一数量的转换进行计数; （b）维持第二时钟信号的转换次数的第一计数; （c）对所述数据信号进行采样，并响应于检测到所述第一计数等于第一预定值而维持所述第二时钟信号的转换次数的第二计数; 以及（d）对数据信号进行采样，并且响应于检测到第二计数等于第二预定值而复位第二计数。

公开(公告)号：US20090074049A1

公开(公告)日：2009-03-19

申请号：US12208898

申请日：2008-09-11

申请人： Gabriel C. Risk ,  Drew G. Doblar ,  Pruthvi A. Chaudhari

发明人： Gabriel C. Risk ,  Drew G. Doblar ,  Pruthvi A. Chaudhari

IPC分类号： H04L27/01

CPC分类号： H04L25/03012

摘要： A method, apparatus, and system for minimizing ringing in a high speed channel between a transmitter and a receiver in a circuit, including a component for initializing an n-tap equalization filter. The n-tap equalization filter includes numerous taps, each associated with each of numerous jitter pulses received from the transmitter at the receiver and over the channel. Many of the jitter pulses are greater than two. Further, each tap occurs at a time-domain point related to a time of a corresponding jitter pulse included within the numerous jitter pulses. Moreover, a component for applying the n-tap equalization filter to a subsequent signal sent over the channel is also included.

摘要翻译： 一种用于最小化电路中的发射机和接收机之间的高速信道中的振铃的方法，装置和系统，包括用于初始化n抽头均衡滤波器的组件。 n抽头均衡滤波器包括多个抽头，每个抽头与接收器处的发射机和信道上的多个抖动脉冲中的每一个相关联。 许多抖动脉冲大于2。 此外，每个抽头发生在与包括在许多抖动脉冲内的相应抖动脉冲的时间相关的时域点。 此外，还包括用于将n抽头均衡滤波器应用于通过信道发送的后续信号的分量。

公开(公告)号：US07533212B1

公开(公告)日：2009-05-12

申请号：US11254948

申请日：2005-10-20

申请人： Drew G. Doblar ,  Gabriel C. Risk ,  Chung-Hsiao Wu

发明人： Drew G. Doblar ,  Gabriel C. Risk ,  Chung-Hsiao Wu

IPC分类号： G06F12/02

CPC分类号： G06F13/426

摘要： A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a switching circuit within a memory chip detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.

摘要翻译： 一种包括存储器模块的存储器系统，包括集成开关电路的存储器芯片。 耦合到存储器模块的存储器控​​制器被配置为启动存储器访问。 当存储器芯片内的开关电路检测到存储器访问时，如果访问不被引导到接收存储器模块的存储器芯片，则切换电路将访问路由到另一个存储器模块，或者如果访问指向 接收存储器模块的存储芯片。 存储器控制器和存储器模块通过双向串行链路耦合。 每个存储器模块可以包括多个开关电路，每个开关电路可以耦合到比存储器模块内的所有存储器芯片少。 开关电路还包括被配置为在传送到存储器芯片之前对数据进行反序列化的电路，以及在发送所接收的数据之前串行从DRAM芯片接收的数据。

公开(公告)号：US08249199B2

公开(公告)日：2012-08-21

申请号：US12342825

申请日：2008-12-23

申请人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

发明人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

IPC分类号： H04L27/06

CPC分类号： H04L7/0062 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/10

摘要： A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.

摘要翻译： 实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。 一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。

公开(公告)号：US08229048B2

公开(公告)日：2012-07-24

申请号：US12208898

申请日：2008-09-11

申请人： Gabriel C. Risk ,  Drew G. Doblar ,  Pruthvi A. Chaudhari

发明人： Gabriel C. Risk ,  Drew G. Doblar ,  Pruthvi A. Chaudhari

IPC分类号： H04B1/10

CPC分类号： H04L25/03012

摘要： A method, apparatus, and system for minimizing ringing in a high speed channel between a transmitter and a receiver in a circuit, including a component for initializing an n-tap equalization filter. The n-tap equalization filter includes numerous taps, each associated with each of numerous jitter pulses received from the transmitter at the receiver and over the channel. Many of the jitter pulses are greater than two. Further, each tap occurs at a time-domain point related to a time of a corresponding jitter pulse included within the numerous jitter pulses. Moreover, a component for applying the n-tap equalization filter to a subsequent signal sent over the channel is also included.

摘要翻译： 一种用于最小化电路中的发射机和接收机之间的高速信道中的振铃的方法，装置和系统，包括用于初始化n抽头均衡滤波器的组件。 n抽头均衡滤波器包括多个抽头，每个抽头与接收器处的发射机和信道上的多个抖动脉冲中的每一个相关联。 许多抖动脉冲大于2。 此外，每个抽头发生在与包括在许多抖动脉冲内的相应抖动脉冲的时间相关的时域点。 此外，还包括用于将n抽头均衡滤波器应用于通过信道发送的后续信号的分量。

公开(公告)号：US08543848B2

公开(公告)日：2013-09-24

申请号：US12886711

申请日：2010-09-21

申请人： Michael Bushue ,  Drew G. Doblar

发明人： Michael Bushue ,  Drew G. Doblar

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： H02M1/36 ,  H02J9/005

摘要： A method for reducing latency using a charging module when activating a power supply unit (PSU) among a plurality of PSUs in a power supply system. The method includes: Receiving, by the PSU from a power input feed, input power; receiving, from a supply bus shared by the plurality of PSUs, a first controlled signal designating a status of the PSU as standby; disabling, in response to the first controlled signal, a switching regulator of the PSU; receiving, from a voltage rail of the supply bus, charge flowing through a resistor of the charging module to maintain a charge of an output capacitor of the switching regulator; receiving a second controlled signal designating the status of the PSU as active; enabling the switching regulator; outputting a voltage from the PSU through the charging module to the voltage rail; and charging the output capacitor using the PSU.

摘要翻译： 一种当在电源系统中的多个PSU中激活电源单元（PSU）时，使用充电模块来减少等待时间的方法。 该方法包括：通过PSU从电源输入馈线接收输入电源; 从所述多个PSU共享的供电总线接收将所述PSU的状态指定为待机的第一受控信号; 响应于第一受控信号，禁用PSU的开关调节器; 从所述电源总线的电压轨道接收流过所述充电模块的电阻器的电荷，以维持所述开关调节器的输出电容器的电荷; 接收指定PSU状态为活动的第二受控信号; 启用开关稳压器; 将来自PSU的电压通过充电模块输出到电压轨; 并使用PSU对输出电容器充电。