公开(公告)号：US08327199B1

公开(公告)日：2012-12-04

申请号：US12718914

申请日：2010-03-05

申请人： Jayabrata Ghosh Dastidar ,  Chiew Khiang Kuit ,  Siew Ling Yeoh ,  Jun Pin Tan ,  Kok Sun Chia ,  Yee Liang Tan ,  Kar Keng Chua

发明人： Jayabrata Ghosh Dastidar ,  Chiew Khiang Kuit ,  Siew Ling Yeoh ,  Jun Pin Tan ,  Kok Sun Chia ,  Yee Liang Tan ,  Kar Keng Chua

IPC分类号： G01R31/28

CPC分类号： G01R31/3172 ,  G01R31/318516

摘要： Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.

摘要翻译： 公开了具有可配置测试引脚的集成电路（IC）和测试IC的方法。 IC具有可配置为测试输入引脚，测试输出引脚或用户I / O引脚的输入/输出（I / O）引脚。 选择器电路用于选择性地将I / O引脚路由和耦合到IC上的各种逻辑块和测试电路。 选择器电路还用于选择性地将用户输出或测试输出耦合到IC上的不同I / O引脚。 开关用于配置选择器电路并在IC内部路由测试信号。 交换机的不同配置决定信号的路由。 来自I / O引脚的测试输入信号可以被路由到IC内的任何测试电路，并且来自测试电路的测试输出信号可以被路由到IC上的任何I / O引脚。

公开(公告)号：US08189362B2

公开(公告)日：2012-05-29

申请号：US13151230

申请日：2011-06-01

申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G11C17/00

CPC分类号： G11C17/18 ,  G11C17/16

摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

公开(公告)号：US20110292711A1

公开(公告)日：2011-12-01

申请号：US13151230

申请日：2011-06-01

申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16

摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

公开(公告)号：US07978493B1

公开(公告)日：2011-07-12

申请号：US12212801

申请日：2008-09-18

申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G11C17/00

CPC分类号： G11C17/18 ,  G11C17/16

摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

公开(公告)号：US08694944B1

公开(公告)日：2014-04-08

申请号：US12643528

申请日：2009-12-21

申请人： Sze Huey Soo ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Sze Huey Soo ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/504 ,  G06F17/5054

摘要： Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.

摘要翻译： 公开了使用从汇编到第一IC设计的输入来计算第二IC设计的可路由度量的方法，计算机程序产品和系统。 第一和第二IC设计是用户电路设计的替代实现选项，例如FPGA和结构化ASIC选项。 关于一个IC设计的路由资源的用户设计需求的信息以及关于在另一个IC设计中的路由资源的预计供应的信息，以产生路由度量。 路由度量可以映射到难度指标，并且可以用于将用户电路的编译调节到第二IC设计或以其他方式使用。

公开(公告)号：US08533250B1

公开(公告)日：2013-09-10

申请号：US12486231

申请日：2009-06-17

申请人： Kok Yoong Foo ,  Yan Jiong Boo ,  Geok Sun Chong ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Kok Yoong Foo ,  Yan Jiong Boo ,  Geok Sun Chong ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G06F7/38 ,  G06F7/00

CPC分类号： G06F7/5443

摘要： Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.

摘要翻译： 公开了具有内置累加器的乘法器的电路和执行与累加相乘的方法。 所公开的电路的实施例包括耦合以接收两个输入的逻辑电路。 逻辑电路能够从接收到的输入产生多个值比特。 在一个实施例中，逻辑电路包括生成多个部分乘积的布斯重新编码器电路。 一组加法器耦合到逻辑电路以接收和总结值位。 加法器将来自加法器块的求和结果相加到先前的累积值，以产生中间和和携带值。 耦合到加法器的累加器接收并存储中间值。

公开(公告)号：US07246339B2

公开(公告)日：2007-07-17

申请号：US11101949

申请日：2005-04-08

申请人： Jinyong Yuan ,  Kar Keng Chua ,  Ji Park

发明人： Jinyong Yuan ,  Kar Keng Chua ,  Ji Park

IPC分类号： G06F17/50 ,  H03K17/693

CPC分类号： G06F17/5045

摘要： Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured ASIC equivalents in the library or for which possibly improved structured ASIC equivalents can now be devised. The new and/or improved structured ASIC equivalents are added to the library, preferably with version information in the case of FPGA logic functions for which more than one structured ASIC equivalent is known.

摘要翻译： 与FPGA逻辑设计相当的结构化ASIC通过利用FPGA逻辑功能的已知结构化ASIC等效的库来产生。 这样一个库可以通过一个过程来扩展，该过程可以搜索逻辑功能的新FPGA逻辑设计，这些逻辑功能在库中尚未具有结构化ASIC等价物，或者现在可以设计出可能改进的结构化ASIC等价物。 新的和/或改进的结构化ASIC等效物被添加到库中，优选地在FPGA逻辑功能的情况下具有已知多于一个结构化ASIC等效物的版本信息。

公开(公告)号：US06599764B1

公开(公告)日：2003-07-29

申请号：US09870354

申请日：2001-05-30

申请人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

发明人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

IPC分类号： H01L2166

CPC分类号： G01R31/2886 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.

摘要翻译： 测试平台被配置为测试具有在第一管芯和第二管芯处的多管芯封装。 测试平台包括一个第一引线，连接到第一个管芯上的VCC输入端。 测试平台还包括连接到第二个芯片上的VCCIO输入的第二引脚。 第二个管芯上的VCC输入端接地。 然后可以使用设置在I / O缓冲器的预驱动器和驱动器之间的控制电路来将第二管芯的I / O引脚三态化。

公开(公告)号：US08261141B1

公开(公告)日：2012-09-04

申请号：US13004133

申请日：2011-01-11

申请人： Kok Heng Choe ,  Edwin Yew Fatt Kok ,  Kar Keng Chua

发明人： Kok Heng Choe ,  Edwin Yew Fatt Kok ,  Kar Keng Chua

IPC分类号： G11C29/00

CPC分类号： H03K5/13 ,  H03K19/173 ,  H03K2005/0013 ,  H03K2005/00143

摘要： Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.

摘要翻译： 通过调整电路操作来调整过程，电压或温度的变化，可编程逻辑中的存储器性能显着增加。 校准电路动态和自动地调节控制信号时序，以补偿实时处理，电压和温度变化。 提供了使用控制块和虚拟模拟概念的反馈系统。

公开(公告)号：US07870513B2

公开(公告)日：2011-01-11

申请号：US11801082

申请日：2007-05-07

申请人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

发明人： Kar Keng Chua ,  Sammy Cheung ,  Hee Kong Phoon ,  Kim Pin Tan ,  Wei Lian Goay

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/177 ,  H03K19/1737

摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

摘要翻译： 通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分 （“LE”）。 实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。 只有使用必要的HLE才能执行每个LE的功能。 每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。