公开(公告)号：US08694944B1

公开(公告)日：2014-04-08

申请号：US12643528

申请日：2009-12-21

申请人： Sze Huey Soo ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Sze Huey Soo ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/504 ,  G06F17/5054

摘要： Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.

摘要翻译： 公开了使用从汇编到第一IC设计的输入来计算第二IC设计的可路由度量的方法，计算机程序产品和系统。 第一和第二IC设计是用户电路设计的替代实现选项，例如FPGA和结构化ASIC选项。 关于一个IC设计的路由资源的用户设计需求的信息以及关于在另一个IC设计中的路由资源的预计供应的信息，以产生路由度量。 路由度量可以映射到难度指标，并且可以用于将用户电路的编译调节到第二IC设计或以其他方式使用。

公开(公告)号：US08151224B1

公开(公告)日：2012-04-03

申请号：US12345187

申请日：2008-12-29

申请人： Boon Jin Ang ,  Kar Keng Chua ,  Choong Kit Wong ,  Kok Yoong Foo ,  Thow Pang Chong

发明人： Boon Jin Ang ,  Kar Keng Chua ,  Choong Kit Wong ,  Kok Yoong Foo ,  Thow Pang Chong

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/64

摘要： A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices. In one embodiment, hybrid cell (H-cell) devices of the HVT mask layer set are HVT devices and some periphery devices of the HVT mask layer set are HVT devices.

摘要翻译： 描述了一种IC设计方法。 在一个实施例中，该方法包括提供从多个掩模层集合中选择掩模层集合的选项，所述多个掩模层集合包括第一掩模层集合和第二掩模层集合，其中第二掩模层集合是 第一掩模层集合的替代掩模层选项。 在一个实施例中，该方法还包括从用户接收从多个掩模层集合中选择掩模层集合的选择。 在一个实施例中，接收发生在IC的设计之后并且在IC的制造之前。 而且，在一个实施例中，多个掩模层组是预定的掩模层集合。 在一个实施例中，第一掩模层集合是标准阈值电压（SVT）掩模层集合，第二掩模层集合是高阈值电压（HVT）掩模层集合。 在一个实施例中，SVT掩模层集合的核心设备是SVT设备，SVT掩模层集合的一些外围设备是HVT设备。 在一个实施例中，HVT掩模层集合的混合小区（H cell）设备是HVT设备，并且HVT掩模层集合的一些外围设备是HVT设备。

公开(公告)号：US08037377B1

公开(公告)日：2011-10-11

申请号：US12127783

申请日：2008-05-27

申请人： Ie Chen Chia ,  Eng Huat Lee ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Ie Chen Chia ,  Eng Huat Lee ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G01R31/28

CPC分类号： G01R31/31716

摘要： A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver channel. The serializer converts the test signals into serial test signals. The deserializer converts the serial test signals into parallel test signals that are transmitted to the built-in self-test circuit.

摘要翻译： 电路包括接收器通道和内置自检电路。 接收器通道具有串行器和解串器。 内置的自检电路在接收机通道测试期间产生并行发送到串行器的测试信号。 串行器将测试信号转换为串行测试信号。 解串器将串行测试信号转换为并行测试信号，传输到内置的自检电路。

公开(公告)号：US07683689B1

公开(公告)日：2010-03-23

申请号：US12082296

申请日：2008-04-10

申请人： Tat Mun Lui ,  Kar Keng Chua ,  Boon Jin Ang ,  Thow Pang Chong ,  Kam Fai Suit

发明人： Tat Mun Lui ,  Kar Keng Chua ,  Boon Jin Ang ,  Thow Pang Chong ,  Kam Fai Suit

IPC分类号： H03H11/26

CPC分类号： H03K5/133

摘要： A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.

摘要翻译： 描述了包括以第一取向取向的第一延迟单元和以第二取向定向的第二延迟单元的延迟电路。 在一个实施例中，第一取向垂直于第二取向。 更具体地，在一个实施例中，第一取向是垂直的，第二取向是水平的。

公开(公告)号：US07242218B2

公开(公告)日：2007-07-10

申请号：US11003586

申请日：2004-12-02

申请人： Rafael Camarota ,  Irfan Rahim ,  Boon Jin Ang ,  Thow Pang Chong

发明人： Rafael Camarota ,  Irfan Rahim ,  Boon Jin Ang ,  Thow Pang Chong

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： G06F15/7867 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17776

摘要： Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.

摘要翻译： 提供了将易失性和非易失性可编程逻辑组合到一个集成电路（IC）中的技术。 IC分为两部分。 可编程逻辑的第一块由存储在片上非易失性存储器中的位来配置。 可编程逻辑的第二块由存储在片外存储器中的位配置。 IC上的IO组的功能在IC的两个逻辑块之间复用。 第一块中的可编程逻辑可以在可配置第二块中的可编程逻辑的几分之一时间内配置和完全运行。 第一块中的可编程逻辑可以配置得足够快，并具有足够的独立性来辅助第二块的配置。 非易失性存储器还可以为诸如加密的用户设计提供安全特征。

公开(公告)号：US08659334B2

公开(公告)日：2014-02-25

申请号：US13543724

申请日：2012-07-06

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US08739099B1

公开(公告)日：2014-05-27

申请号：US12176379

申请日：2008-07-20

申请人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

发明人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031 ,  G06F2217/62

摘要： A method for determining clock uncertainties is provided. The method includes identifying clock transfer types between registers from an integrated circuit design and identifying contributors to the clock uncertainties for each of the clock transfers. The jitter associated with each identified contributor is calculated for both set-up time and hold time. This calculated jitter is incorporated into a slack calculation to determine whether timing constraints are met for a circuit design.

摘要翻译： 提供了一种确定时钟不确定度的方法。 该方法包括从集成电路设计中识别寄存器之间的时钟传输类型，并且识别每个时钟传输的时钟不确定性的贡献者。 针对建立时间和保持时间计算与每个识别的贡献者相关联的抖动。 该计算的抖动被并入到松弛计算中以确定电路设计是否满足时序约束。

公开(公告)号：US07233189B1

公开(公告)日：2007-06-19

申请号：US10996592

申请日：2004-11-24

申请人： Boon Jin Ang ,  Thow Pang Chong

发明人： Boon Jin Ang ,  Thow Pang Chong

IPC分类号： H03K3/00 ,  G06F17/50

CPC分类号： G06F1/10

摘要： Signal transmission circuitry on an integrated circuit ameliorates the effects of possible inequality in rise and fall times of buffer circuits along the transmission circuitry by providing at least one of the buffer circuits as an inverting buffer circuit and at least one other of the buffer circuits as a non-inverting buffer circuit. The invention may be of particular interest for use in clock signal distribution networks on integrated circuits such as programmable logic devices.

摘要翻译： 集成电路上的信号传输电路通过将缓冲电路中的至少一个作为反相缓冲电路和至少另一个缓冲电路来改善沿着传输电路的缓冲电路的上升和下降时间可能的不等式的影响，作为 非反相缓冲电路。 本发明可以特别关注于集成电路（例如可编程逻辑器件）上的时钟信号分配网络。

公开(公告)号：US08533250B1

公开(公告)日：2013-09-10

申请号：US12486231

申请日：2009-06-17

申请人： Kok Yoong Foo ,  Yan Jiong Boo ,  Geok Sun Chong ,  Boon Jin Ang ,  Kar Keng Chua

发明人： Kok Yoong Foo ,  Yan Jiong Boo ,  Geok Sun Chong ,  Boon Jin Ang ,  Kar Keng Chua

IPC分类号： G06F7/38 ,  G06F7/00

CPC分类号： G06F7/5443

摘要： Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.

摘要翻译： 公开了具有内置累加器的乘法器的电路和执行与累加相乘的方法。 所公开的电路的实施例包括耦合以接收两个输入的逻辑电路。 逻辑电路能够从接收到的输入产生多个值比特。 在一个实施例中，逻辑电路包括生成多个部分乘积的布斯重新编码器电路。 一组加法器耦合到逻辑电路以接收和总结值位。 加法器将来自加法器块的求和结果相加到先前的累积值，以产生中间和和携带值。 耦合到加法器的累加器接收并存储中间值。

公开(公告)号：US06599764B1

公开(公告)日：2003-07-29

申请号：US09870354

申请日：2001-05-30

申请人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

发明人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

IPC分类号： H01L2166

CPC分类号： G01R31/2886 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.

摘要翻译： 测试平台被配置为测试具有在第一管芯和第二管芯处的多管芯封装。 测试平台包括一个第一引线，连接到第一个管芯上的VCC输入端。 测试平台还包括连接到第二个芯片上的VCCIO输入的第二引脚。 第二个管芯上的VCC输入端接地。 然后可以使用设置在I / O缓冲器的预驱动器和驱动器之间的控制电路来将第二管芯的I / O引脚三态化。