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    Data encoding scheme to reduce sense current
    1.
    发明授权
    Data encoding scheme to reduce sense current 有权
    减少感应电流的数据编码方案

    公开(公告)号：US08189362B2

    公开(公告)日：2012-05-29

    申请号：US13151230

    申请日：2011-06-01

    申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G11C17/00

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

    摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

    DATA ENCODING SCHEME TO REDUCE SENSE CURRENT
    2.
    发明申请
    DATA ENCODING SCHEME TO REDUCE SENSE CURRENT 有权
    数据编码方案降低感应电流

    公开(公告)号：US20110292711A1

    公开(公告)日：2011-12-01

    申请号：US13151230

    申请日：2011-06-01

    申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G11C17/16

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

    摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

    Data encoding scheme to reduce sense current
    3.
    发明授权
    Data encoding scheme to reduce sense current 有权
    减少感应电流的数据编码方案

    公开(公告)号：US07978493B1

    公开(公告)日：2011-07-12

    申请号：US12212801

    申请日：2008-09-18

    申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G11C17/00

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

    摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

    Method of designing integrated circuits including providing an option to select a mask layer set
    4.
    发明授权
    Method of designing integrated circuits including providing an option to select a mask layer set 有权
    设计集成电路的方法，包括提供选择掩模层集合的选项

    公开(公告)号：US08151224B1

    公开(公告)日：2012-04-03

    申请号：US12345187

    申请日：2008-12-29

    申请人： Boon Jin Ang ,  Kar Keng Chua ,  Choong Kit Wong ,  Kok Yoong Foo ,  Thow Pang Chong

    发明人： Boon Jin Ang ,  Kar Keng Chua ,  Choong Kit Wong ,  Kok Yoong Foo ,  Thow Pang Chong

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/64

    摘要： A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices. In one embodiment, hybrid cell (H-cell) devices of the HVT mask layer set are HVT devices and some periphery devices of the HVT mask layer set are HVT devices.

    摘要翻译： 描述了一种IC设计方法。 在一个实施例中，该方法包括提供从多个掩模层集合中选择掩模层集合的选项，所述多个掩模层集合包括第一掩模层集合和第二掩模层集合，其中第二掩模层集合是 第一掩模层集合的替代掩模层选项。 在一个实施例中，该方法还包括从用户接收从多个掩模层集合中选择掩模层集合的选择。 在一个实施例中，接收发生在IC的设计之后并且在IC的制造之前。 而且，在一个实施例中，多个掩模层组是预定的掩模层集合。 在一个实施例中，第一掩模层集合是标准阈值电压（SVT）掩模层集合，第二掩模层集合是高阈值电压（HVT）掩模层集合。 在一个实施例中，SVT掩模层集合的核心设备是SVT设备，SVT掩模层集合的一些外围设备是HVT设备。 在一个实施例中，HVT掩模层集合的混合小区（H cell）设备是HVT设备，并且HVT掩模层集合的一些外围设备是HVT设备。

    Techniques for performing built-in self-test of receiver channel having a serializer
    5.
    发明授权
    Techniques for performing built-in self-test of receiver channel having a serializer 有权
    用于执行具有串行器的接收机通道的内置自检的技术

    公开(公告)号：US08037377B1

    公开(公告)日：2011-10-11

    申请号：US12127783

    申请日：2008-05-27

    申请人： Ie Chen Chia ,  Eng Huat Lee ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Ie Chen Chia ,  Eng Huat Lee ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31716

    摘要： A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver channel. The serializer converts the test signals into serial test signals. The deserializer converts the serial test signals into parallel test signals that are transmitted to the built-in self-test circuit.

    摘要翻译： 电路包括接收器通道和内置自检电路。 接收器通道具有串行器和解串器。 内置的自检电路在接收机通道测试期间产生并行发送到串行器的测试信号。 串行器将测试信号转换为串行测试信号。 解串器将串行测试信号转换为并行测试信号，传输到内置的自检电路。

    Predicting routability of integrated circuits
    6.
    发明授权
    Predicting routability of integrated circuits 有权
    预测集成电路的可布线性

    公开(公告)号：US08694944B1

    公开(公告)日：2014-04-08

    申请号：US12643528

    申请日：2009-12-21

    申请人： Sze Huey Soo ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Sze Huey Soo ,  Thow Pang Chong ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/504 ,  G06F17/5054

    摘要： Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.

    摘要翻译： 公开了使用从汇编到第一IC设计的输入来计算第二IC设计的可路由度量的方法，计算机程序产品和系统。 第一和第二IC设计是用户电路设计的替代实现选项，例如FPGA和结构化ASIC选项。 关于一个IC设计的路由资源的用户设计需求的信息以及关于在另一个IC设计中的路由资源的预计供应的信息，以产生路由度量。 路由度量可以映射到难度指标，并且可以用于将用户电路的编译调节到第二IC设计或以其他方式使用。

    Multiplier with built-in accumulator
    7.
    发明授权
    Multiplier with built-in accumulator 有权
    带内置蓄能器的乘数

    公开(公告)号：US08533250B1

    公开(公告)日：2013-09-10

    申请号：US12486231

    申请日：2009-06-17

    申请人： Kok Yoong Foo ,  Yan Jiong Boo ,  Geok Sun Chong ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Kok Yoong Foo ,  Yan Jiong Boo ,  Geok Sun Chong ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G06F7/38 ,  G06F7/00

    CPC分类号： G06F7/5443

    摘要： Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.

    摘要翻译： 公开了具有内置累加器的乘法器的电路和执行与累加相乘的方法。 所公开的电路的实施例包括耦合以接收两个输入的逻辑电路。 逻辑电路能够从接收到的输入产生多个值比特。 在一个实施例中，逻辑电路包括生成多个部分乘积的布斯重新编码器电路。 一组加法器耦合到逻辑电路以接收和总结值位。 加法器将来自加法器块的求和结果相加到先前的累积值，以产生中间和和携带值。 耦合到加法器的累加器接收并存储中间值。

    Isolation testing scheme for multi-die packages
    8.
    发明授权
    Isolation testing scheme for multi-die packages 失效
    多芯片封装的隔离测试方案

    公开(公告)号：US06599764B1

    公开(公告)日：2003-07-29

    申请号：US09870354

    申请日：2001-05-30

    申请人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

    发明人： Boon Jin Ang ,  Sammy Cheung ,  Kar Keng Chua

    IPC分类号： H01L2166

    CPC分类号： G01R31/2886 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.

    摘要翻译： 测试平台被配置为测试具有在第一管芯和第二管芯处的多管芯封装。 测试平台包括一个第一引线，连接到第一个管芯上的VCC输入端。 测试平台还包括连接到第二个芯片上的VCCIO输入的第二引脚。 第二个管芯上的VCC输入端接地。 然后可以使用设置在I / O缓冲器的预驱动器和驱动器之间的控制电路来将第二管芯的I / O引脚三态化。

    Delay circuit with delay cells in different orientations
    9.
    发明授权
    Delay circuit with delay cells in different orientations 有权
    延迟电路具有不同方向的延迟单元

    公开(公告)号：US07683689B1

    公开(公告)日：2010-03-23

    申请号：US12082296

    申请日：2008-04-10

    申请人： Tat Mun Lui ,  Kar Keng Chua ,  Boon Jin Ang ,  Thow Pang Chong ,  Kam Fai Suit

    发明人： Tat Mun Lui ,  Kar Keng Chua ,  Boon Jin Ang ,  Thow Pang Chong ,  Kam Fai Suit

    IPC分类号： H03H11/26

    CPC分类号： H03K5/133

    摘要： A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.

    摘要翻译： 描述了包括以第一取向取向的第一延迟单元和以第二取向定向的第二延迟单元的延迟电路。 在一个实施例中，第一取向垂直于第二取向。 更具体地，在一个实施例中，第一取向是垂直的，第二取向是水平的。