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6 条记录 (耗时 0.026 秒)

    ASSIST CIRCUIT FOR MEMORY
    1.
    发明申请
    ASSIST CIRCUIT FOR MEMORY 有权
    记忆辅助电路

    公开(公告)号：US20150279438A1

    公开(公告)日：2015-10-01

    申请号：US14229767

    申请日：2014-03-28

    申请人： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    发明人： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

    IPC分类号： G11C7/12 ,  G11C17/16 ,  G11C7/22

    CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

    摘要： Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

    摘要翻译： 实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。 例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。 辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。 另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。 辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

    LOW POWER TRANSIENT VOLTAGE COLLAPSE APPARATUS AND METHOD FOR A MEMORY CELL
    3.
    发明申请
    LOW POWER TRANSIENT VOLTAGE COLLAPSE APPARATUS AND METHOD FOR A MEMORY CELL 有权
    低功耗瞬态电压放大器和存储器单元的方法

    公开(公告)号：US20140340977A1

    公开(公告)日：2014-11-20

    申请号：US13976403

    申请日：2013-05-16

    申请人： Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

    发明人： Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

    IPC分类号： G11C5/14 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C5/147 ,  G11C11/413 ,  G11C11/414 ,  G11C11/417

    摘要： Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.

    摘要翻译： 描述了一种在写入辅助操作期间消耗低功率的存储器写入辅助装置。 该装置包括：电源节点; 可操作以调节所述电源节点上的电压的装置; 以及耦合到所述电源节点的反馈单元，所述反馈单元响应于所述电源节点上的电压的电压电平来控制所述装置。

    OPERATION AWARE AUTO-FEEDBACK SRAM
    4.
    发明申请
    OPERATION AWARE AUTO-FEEDBACK SRAM 有权
    操作注意自动反馈SRAM

    公开(公告)号：US20140169077A1

    公开(公告)日：2014-06-19

    申请号：US13991423

    申请日：2011-12-31

    申请人： Pramod Kolar ,  Eric A. Karl

    发明人： Pramod Kolar ,  Eric A. Karl

    IPC分类号： G11C11/412 ,  G11C11/419

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.

    摘要翻译： 描述了静态随机存取存储器。 SRAM包括存储单元和电压源，以在写入操作期间向存储单元提供降低的电压。 SRAM单元包括第一通道栅极和第二栅极。 第一电阻器耦合在第一通道栅极和存储单元的第一侧之间。 第二电阻器耦合在第二通道栅极和存储单元的第二侧之间。

    Operation aware auto-feedback SRAM
    5.
    发明授权
    Operation aware auto-feedback SRAM 有权

    公开(公告)号：US09767890B2

    公开(公告)日：2017-09-19

    申请号：US13991423

    申请日：2011-12-31

    申请人： Pramod Kolar ,  Eric A. Karl

    发明人： Pramod Kolar ,  Eric A. Karl

    IPC分类号： G11C11/412 ,  G11C11/419

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.