Method of making a gated isolated structure
    1.
    发明授权
    Method of making a gated isolated structure 失效
    制作门控隔离结构的方法

    公开(公告)号:US4849366A

    公开(公告)日:1989-07-18

    申请号:US144272

    申请日:1988-01-15

    CPC分类号: H01L21/765 Y10S438/953

    摘要: The invention relates to a radiation hardened (R-H) bulk complementary metal oxide semiconductor (CMOS) isolation structure and a process for its formation. The isolation structure may be automatically generated from the original thin oxide layer of any commercial product by computer aided design and basically comprises a grounded MOS gate surrounding the active areas. The grounded MOS gate replaces the conventional LOCOS field oxide and consists of novel oxide-silicon nitride-oxynitride gate insulator and a CVD polysilicon film. The radiation resistance of this gated isolated structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuit (.ltoreq.2 .mu.m design rule).

    Gated isolated structure
    2.
    发明授权
    Gated isolated structure 失效
    门控隔离结构

    公开(公告)号:US4937756A

    公开(公告)日:1990-06-26

    申请号:US300582

    申请日:1989-01-23

    IPC分类号: H01L21/765

    摘要: The invention relates to a radiation-hardened (R-H) bulk CMOS process which is compatible with DRAM production and a specific gated isolation structure (GIS). The GIS structure consists of a novel oxide-silicon nitride-oxynitride gate insulator and a LPCVD polysilicon gate. A simple but automatically generating process for creating GIS directly from an original non-R-H device is also described. This generating process is fast and can revise any commercial products to a R-H version. The GIS is always shunted to Vss potential of the circuit chip to assure R-H capability. The grounded GIS structure replaces conventional LOCOS field oxide, which suffers from large threshold voltage shift when exposed to irradiation. Radiation resistance of this gated isolation structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuits (.ltoreq.2um design rule).

    摘要翻译: 本发明涉及与DRAM生产和特定的门控隔离结构(GIS)兼容的辐射硬化(R-H)体CMOS工艺。 GIS结构由新型氧化物 - 氮化硅 - 氮氧化物栅极绝缘体和LPCVD多晶硅栅极组成。 还描述了一种用于从原始非R-H设备直接创建GIS的简单但自动生成的过程。 这个生成过程很快,可以将任何商业产品修改为R-H版本。 GIS总是分流到电路芯片的Vss电位,以确保R-H能力。 接地的GIS结构代替常规的LOCOS场氧化物,当暴露于照射时,其具有大的阈值电压偏移。 该门控隔离结构(GIS)的抗辐射性适用于放射免疫VLSI集成电路(

    Building and method for manufacture of integrated semiconductor circuit
devices
    3.
    发明授权
    Building and method for manufacture of integrated semiconductor circuit devices 失效
    集成半导体电路器件的制造和制造方法

    公开(公告)号:US5350336A

    公开(公告)日:1994-09-27

    申请号:US51381

    申请日:1993-04-23

    摘要: A manufacturing plant is described for producing semiconductors that will function at a low production level during the initial phase. The plant can be expanded to provide a greater production volume with minimum additional investment, minimum disruption to the existing manufacturing line, and can be done quickly at minimum cost. Also described is a method for building a manufacturing plant for integrated circuit devices that can be operated at a low level during the initial phase, and provides for an efficient and rapid expansion to a higher level of manufacturing with minimum cost, and disruption to the existing line.

    摘要翻译: 描述了一种制造工厂,用于生产在初始阶段将以低生产水平起作用的半导体。 该工厂可以扩大,提供更大的生产量,最小的额外投资,最小化现有生产线的中断,并可以以最低的成本快速完成。 还描述了一种用于构建用于集成电路器件的制造工厂的方法,其可以在初始阶段期间以较低的水平运行,并以最小的成本提供高效率和快速地扩展到更高水平的制造,并且破坏现有的 线。