公开(公告)号：US06323541B1

公开(公告)日：2001-11-27

申请号：US09110986

申请日：1998-07-07

申请人： Chen-Der Huang ,  Hsing-Hai Chen

发明人： Chen-Der Huang ,  Hsing-Hai Chen

IPC分类号： H01L23495

CPC分类号： H01L24/06 ,  H01L23/49524 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

摘要： A structure of manufacture of a semiconductor die on a lead-on-chip (LOC) packaging using a flexible copper plated tape and a standard lead frame is disclosed. A semiconductor die with bonding pads in the center is interconnected to a flexible copper plated tape by copper trace, solder bumps, or gold bump. The flexible copper plated tape is then placed on top of and attached to a standard lead frame. The configuration of a flexible copper plated tape, such material includes polymide tape, matches the configuration of a lead frame that allows the use of a standard outer lead frame. The configuration of a polymide tape provides greater flexibility in the placement of bonding pads anywhere on a semiconductor die without limiting the bonding pads to be placed in the center of a semiconductor die.

摘要翻译： 公开了使用柔性镀铜带和标准引线框在芯片上（LOC）封装上制造半导体管芯的结构。 具有中心的接合焊盘的半导体管芯通过铜迹线，焊料凸点或金凸块与柔性镀铜带相互连接。 然后将柔性镀铜带放置在标准引线框架的顶部并附接到标准引线框架上。 柔性镀铜带的构造，这种材料包括聚酰亚胺胶带，匹配允许使用标准外部引线框架的引线框架的结构。 多晶硅胶带的配置在半导体管芯上的任何地方的焊盘的放置上提供了更大的灵活性，而不限制要放置在半导体管芯的中心的接合焊盘。

公开(公告)号：US20060103006A1

公开(公告)日：2006-05-18

申请号：US10988100

申请日：2004-11-12

申请人： Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

发明人： Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

IPC分类号： H01L23/06

CPC分类号： H05K1/0271 ,  H01L23/13 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

摘要： A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.

公开(公告)号：US20060170114A1

公开(公告)日：2006-08-03

申请号：US11047060

申请日：2005-01-31

申请人： Chao-Yuan Su ,  Chen-Der Huang ,  Chien-Hsiun Lee ,  Hsin-Hui Lee

发明人： Chao-Yuan Su ,  Chen-Der Huang ,  Chien-Hsiun Lee ,  Hsin-Hui Lee

IPC分类号： H01L23/52

CPC分类号： H01L21/288 ,  H01L21/76843 ,  H01L21/7685 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/484 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/78301 ,  H01L2224/85375 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of bonding a conductive wire on copper pad is presented. A passivation layer is formed on a copper pad. The passivation layer has an opening through which at least a portion of the copper pad is exposed. A nickel-copper-phosphorous (Ni—Cu—P) layer is formed on the copper pad by electroless plating. A conductive wire is bonded through the Ni—Cu—P layer and to the copper pad. The Ni—Cu—P layer protects the underline copper pads from oxidation so that a better bonding can be formed between the conductive wire and the copper pad.

摘要翻译： 提出了一种将导线接合在铜垫上的方法。 钝化层形成在铜垫上。 钝化层具有开口，至少一部分铜焊盘露出。 通过化学镀在铜焊盘上形成镍 - 铜 - 磷（Ni-Cu-P）层。 导线通过Ni-Cu-P层和铜垫结合。 Ni-Cu-P层保护底线铜焊盘不被氧化，从而可以在导线和铜焊盘之间形成更好的接合。

公开(公告)号：US07105920B2

公开(公告)日：2006-09-12

申请号：US10988100

申请日：2004-11-12

申请人： Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

发明人： Chao-Yuan Su ,  Chen-Der Huang ,  Pei-Haw Tsao ,  Chuen-Jye Lin

IPC分类号： H01L23/12

CPC分类号： H05K1/0271 ,  H01L23/13 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K2201/0187 ,  H05K2201/068 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

摘要： A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.

摘要翻译： 提供了提高芯片封装可靠性的基板设计。 芯片封装包括在凹部中形成有陶瓷层的基板。 模具附着在陶瓷层上的衬底上。 基板可以附接到印刷电路板。 衬底可以通过在诸如由有机电介质材料形成的多层衬底的衬底中形成凹陷来制造。 然后将陶瓷层固定在凹槽中的基底上。 可以将模具连接到陶瓷层，并且基板可以附接到印刷电路板。